PMOS Pass Gate Local Bitline SRAM Architecture with Virtual V_{\mathrm{SS}} for Near-Threshold Operation

Juhyun Park; Tae Woo Oh; Seong Ook Jung

doi:10.1109/TVLSI.2019.2963704

PMOS Pass Gate Local Bitline SRAM Architecture with Virtual V_{\mathrm{SS}} for Near-Threshold Operation

Juhyun Park, Tae Woo Oh, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM) architecture is proposed to reduce the read delay and resolve the half-select issue with a small area overhead. Virtual V_{\mathrm {SS}} write assist is included in the architecture to improve write ability. In 22-nm fin-shaped FET (FinFET) technology, the proposed PPG LB architecture achieves an improved read delay and reduced total operation energy by 44% and 65%, respectively, at 0.4 V, compared to the full-swing LB (FSLB) SRAM architecture.

Original language	English
Article number	8966589
Pages (from-to)	1079-1083
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	28
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2019.2963704
Publication status	Published - 2020 Apr

Bibliographical note

Publisher Copyright:
© 1993-2012 IEEE.

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2019.2963704

Cite this

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title = "PMOS Pass Gate Local Bitline SRAM Architecture with Virtual V_{\mathrm{SS}} for Near-Threshold Operation",

abstract = "In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM) architecture is proposed to reduce the read delay and resolve the half-select issue with a small area overhead. Virtual V_{\mathrm {SS}} write assist is included in the architecture to improve write ability. In 22-nm fin-shaped FET (FinFET) technology, the proposed PPG LB architecture achieves an improved read delay and reduced total operation energy by 44% and 65%, respectively, at 0.4 V, compared to the full-swing LB (FSLB) SRAM architecture.",

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PMOS Pass Gate Local Bitline SRAM Architecture with Virtual V_{\mathrm{SS}} for Near-Threshold Operation

Abstract

Bibliographical note

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