Phase/frequency detectors for high-speed PLL applications

Sang O. Jeon; Tae Sik Cheung; Woo Young Choi

doi:10.1049/el:19981493

Phase/frequency detectors for high-speed PLL applications

Sang O. Jeon, Tae Sik Cheung, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

7 Citations (Scopus)

Abstract

Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32ns and the other a reset time of 0.03ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8μm CMOS process parameters.

Original language	English
Pages (from-to)	2120-2121
Number of pages	2
Journal	Electronics Letters
Volume	34
Issue number	22
DOIs	https://doi.org/10.1049/el:19981493
Publication status	Published - 1998 Oct 29

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:19981493

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title = "Phase/frequency detectors for high-speed PLL applications",

abstract = "Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32ns and the other a reset time of 0.03ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8μm CMOS process parameters.",

author = "Jeon, {Sang O.} and Cheung, {Tae Sik} and Choi, {Woo Young}",

year = "1998",

month = oct,

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doi = "10.1049/el:19981493",

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journal = "Electronics Letters",

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publisher = "Institution of Engineering and Technology",

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T1 - Phase/frequency detectors for high-speed PLL applications

AU - Jeon, Sang O.

AU - Cheung, Tae Sik

AU - Choi, Woo Young

PY - 1998/10/29

Y1 - 1998/10/29

N2 - Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32ns and the other a reset time of 0.03ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8μm CMOS process parameters.

AB - Two new phase/frequency detectors (PFDs) are proposed that can overcome the speed and jitter limitations of conventional PFD schemes. One of the proposed circuits has a reset time of 0.32ns and the other a reset time of 0.03ns during the phase-locked loop capture process, according to HSPICE simulation with 0.8μm CMOS process parameters.

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DO - 10.1049/el:19981493

M3 - Article

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SP - 2120

EP - 2121

JO - Electronics Letters

JF - Electronics Letters

IS - 22

ER -

Phase/frequency detectors for high-speed PLL applications

Abstract

All Science Journal Classification (ASJC) codes

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