Performance Optimization and Improvement of Silicon Avalanche Photodetectors in Standard CMOS Technology

Myung Jae Lee; Woo Young Choi

doi:10.1109/JSTQE.2017.2754359

Performance Optimization and Improvement of Silicon Avalanche Photodetectors in Standard CMOS Technology

Myung Jae Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs' structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.

Original language	English
Article number	8047267
Journal	IEEE Journal of Selected Topics in Quantum Electronics
Volume	24
Issue number	2
DOIs	https://doi.org/10.1109/JSTQE.2017.2754359
Publication status	Published - 2018 Mar 1

Bibliographical note

Funding Information:
Manuscript received May 29, 2017; revised September 12, 2017; accepted September 13, 2017. Date of publication September 20, 2017; date of current version October 19, 2017. This work was supported in part by the National Research Foundation of Korea grant funded by the Korean Ministry of Science, ICT and Future Planning under Grant 2015R1A2A2A01007772 and in part by the Materials and Parts Technology R&D Program funded by the Korean Ministry of Trade, Industry & Energy under Project 10065666.

Publisher Copyright:
© 1995-2012 IEEE.

All Science Journal Classification (ASJC) codes

Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

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10.1109/JSTQE.2017.2754359

Cite this

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abstract = "This paper discusses design optimization for silicon avalanche photodetectors (APDs) fabricated in standard complementary metal-oxide-semiconductor (CMOS) technology in order to achieve the highest possible performance. Such factors as PN junctions, guard ring structures, active areas, and back-end structures are considered for the optimization. CMOS-APDs reflecting varying aspects of these factors are fabricated and their performances are characterized. In addition, their characteristics are analyzed with technology computer-aided-design simulations and equivalent circuit models. From these investigations, dominant factors that influence the CMOS-APD performance are identified. Furthermore, three different techniques enabling further performance improvements of CMOS-APDs are investigated, which are spatial-modulation, carrier-acceleration, and multijunction techniques. The state-of-the-art CMOS-APDs' structures and performances are presented and compared, and the best optimized CMOS-APD is proposed. These results should be extremely useful for realizing optimal silicon APDs in standard CMOS technology for various applications.",

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Performance Optimization and Improvement of Silicon Avalanche Photodetectors in Standard CMOS Technology

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