Performance Analysis of Criticality-Aware Out-of-Order Cores for Exploiting MLP

Modern out-of-order processors have improved their performance by leveraging instruction-level parallelism (ILP). Unfortunately, the performance of out-of-order cores are often limited by the latency gap between the cores and their memory hierarchies. One way to overcome this problem is extracting memory-level parallelism (MLP) by issuing long-latency memory instructions as fast as possible to reduce the effective stall cycles of load-dependent instructions. Prior works have suggested prioritizing critical instructions in slice-out-of-order cores, which comprises of multiple in-order issue queues, but they do not explore their effectiveness in out-of-order cores. In this paper, we analyze the performance impact of a criticality-aware out-of-order core that prioritizes critical instructions using iterative backward dependency analysis (IBDA). For this, we compare the performance of the proposed design with a conventional out-of-order core using a cycle-level x86 simulator. Our results show that prioritizing critical instructions with IBDA is not effective for boosting MLP in out-of-order cores, compared to the slice-out-of-order core designs.