Parasitic RC Aware Delay Corner Model for Sub-10-nm Logic Circuit Design

Tae Hoon Choi, Tae Woo Oh, Seong Ook Jung

Research output: Contribution to journalArticlepeer-review


In this paper, we propose a new statistical corner model for the precise variation analysis of CMOS logic gate delay. The conventional corner model includes pessimism in its prediction of delay variation as a result of inadequate statistical consideration of device characteristics. Therefore, to develop an accurate delay corner model, we analytically derive corner modeling targets for device characteristics, which are statistically shrunk when considering the variation and the correlation of transistor and parasitic resistance and capacitance (RC). Then, the derived targets are obtained by multiplying the conventional corner parameters using the newly proposed corner scaling factors. Simulation results verify that the corner model fitted to the proposed targets accurately predicts the three standard deviation limits of delay variation. To implement the parasitic RC aware delay corner in compact models of the process design kit, an artificial neural network is used to model the complex relationship between the parasitic RC and the delay corner model. The delay variations predicted by the proposed model match well with the Monte Carlo simulation results at various simulation conditions, unlike the conventional corner model, which introduces pessimism.

Original languageEnglish
Article number8558694
Pages (from-to)191-199
Number of pages9
JournalIEEE Transactions on Electron Devices
Issue number1
Publication statusPublished - 2019 Jan

Bibliographical note

Publisher Copyright:
© 1963-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


Dive into the research topics of 'Parasitic RC Aware Delay Corner Model for Sub-10-nm Logic Circuit Design'. Together they form a unique fingerprint.

Cite this