TY - GEN
T1 - Parallel transpose of matrix multiplication based on the tiling algorithms
AU - Kim, Minwoo
AU - Jang, Yong J.
AU - Ro, Won W.
PY - 2011
Y1 - 2011
N2 - This paper introduces a useful technique which can be used in a parallel matrix multiplication with the tiling method. Firstly, we exploit the effect of the matrix transpose for the tiling algorithm compared to the standard tiling algorithm. The experimental results show that the transpose tiling algorithm is more efficient than the standard tiling algorithm in most usable tile sizes. Moreover, we propose a parallel transpose tiling algorithm which is further developed from transpose tiling algorithm. Parallel transpose tiling algorithm reduces the overhead of transpose operation by distributing the matrix over multiple threads. As a result, the parallel transpose tiling algorithm is up to 4.76% and 6.61% faster than the original transpose tiling algorithm on Core2 9400 and Phenom 9550 processors, respectively.
AB - This paper introduces a useful technique which can be used in a parallel matrix multiplication with the tiling method. Firstly, we exploit the effect of the matrix transpose for the tiling algorithm compared to the standard tiling algorithm. The experimental results show that the transpose tiling algorithm is more efficient than the standard tiling algorithm in most usable tile sizes. Moreover, we propose a parallel transpose tiling algorithm which is further developed from transpose tiling algorithm. Parallel transpose tiling algorithm reduces the overhead of transpose operation by distributing the matrix over multiple threads. As a result, the parallel transpose tiling algorithm is up to 4.76% and 6.61% faster than the original transpose tiling algorithm on Core2 9400 and Phenom 9550 processors, respectively.
UR - http://www.scopus.com/inward/record.url?scp=80053621938&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80053621938&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2011.6026311
DO - 10.1109/MWSCAS.2011.6026311
M3 - Conference contribution
AN - SCOPUS:80053621938
SN - 9781612848570
T3 - Midwest Symposium on Circuits and Systems
BT - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
T2 - 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Y2 - 7 August 2011 through 10 August 2011
ER -