Parallel transpose of matrix multiplication based on the tiling algorithms

Minwoo Kim, Yong J. Jang, Won W. Ro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper introduces a useful technique which can be used in a parallel matrix multiplication with the tiling method. Firstly, we exploit the effect of the matrix transpose for the tiling algorithm compared to the standard tiling algorithm. The experimental results show that the transpose tiling algorithm is more efficient than the standard tiling algorithm in most usable tile sizes. Moreover, we propose a parallel transpose tiling algorithm which is further developed from transpose tiling algorithm. Parallel transpose tiling algorithm reduces the overhead of transpose operation by distributing the matrix over multiple threads. As a result, the parallel transpose tiling algorithm is up to 4.76% and 6.61% faster than the original transpose tiling algorithm on Core2 9400 and Phenom 9550 processors, respectively.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - 2011
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: 2011 Aug 72011 Aug 10

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Country/TerritoryKorea, Republic of
CitySeoul
Period11/8/711/8/10

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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