Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

Chulwoo Kim; Seong Ook Jung; Kwang Hyun Baek; Sung Mo Kang

doi:10.1109/ISCAS.2000.857206

Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

Chulwoo Kim, Seong Ook Jung, Kwang Hyun Baek, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Citations (Scopus)

Abstract

In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

Original language	English
Pages (from-to)	I-756-I-759
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.2000.857206
Publication status	Published - 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 - Geneva, Switz, Switzerland Duration: 2000 May 28 → 2000 May 31

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ISCAS.2000.857206

Cite this

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title = "Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic",

abstract = "In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.",

author = "Chulwoo Kim and Jung, {Seong Ook} and Baek, {Kwang Hyun} and Kang, {Sung Mo}",

year = "2000",

doi = "10.1109/ISCAS.2000.857206",

language = "English",

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pages = "I--756--I--759",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the IEEE 2000 International Symposium on Circuits and Systems, ISCAS 2000 ; Conference date: 28-05-2000 Through 31-05-2000",

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TY - JOUR

T1 - Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

AU - Kim, Chulwoo

AU - Jung, Seong Ook

AU - Baek, Kwang Hyun

AU - Kang, Sung Mo

PY - 2000

Y1 - 2000

N2 - In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

AB - In this paper, we describe Parallel Dynamic Logic (PDL) which exhibits high speed, no charge sharing problem. PDL uses only parallel-connected transistors for logic evaluation and is a good candidate for high-speed low-voltage operation. It has less back-bias effect compared to other logic styles which use stacked transistors. Furthermore, PDL needs no signal ordering nor tapering. PDL with speed-enhanced skewed static logic renders straightforward logic synthesis without area penalty due to logic duplication. Our experimental results on two 32-bit carry look ahead adders using 0.25 μm CMOS technology showed that PDL with speed-enhanced skewed static (SSS) logic improves performance over clock-delayed (CD)-domino by 15-27% and power×delay by 20-37%.

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DO - 10.1109/ISCAS.2000.857206

M3 - Conference article

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VL - 1

SP - I-756-I-759

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

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Y2 - 28 May 2000 through 31 May 2000

ER -

Parallel Dynamic Logic (PDL) with speed-enhanced skewed static (SSS) logic

Abstract

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