P-56: Design of gate integrated circuit using IGZO thin film transistors for TFT-LCD panel

Sangjin Jeon; Gwangbum Ko; Jongwoong Chang; Samjin Hwang; Jaemin Myoung

doi:10.1889/1.3621078

P-56: Design of gate integrated circuit using IGZO thin film transistors for TFT-LCD panel

Sangjin Jeon, Gwangbum Ko, Jongwoong Chang, Samjin Hwang, Jaemin Myoung

Department of Materials Science and Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

This thesis deals with the method to improve the gate driver stability of large sized IGZO TFT panel. The proposed Gate driver circuit was designed for 26-inch HD LCD Panel and the circuit has been designed considering the electrical characteristic of instability under the bias stress and temperature This circuit consists of twenty TFT using two clock signals such as CK1,CK2 (Von) and 1 power signals such as VSS (Voff), and new circuit with double inverter suppress the ripple occurrence for every time except actuating time that the signal of the gate line is revealed. By applying the proposed new circuit, the H-SPICE simulation was performed. TFT in integrated circuit can be stable in the low frequency drive (48 Hz) althought δVth was 29 V and It could be applicable to the threshold frequency of 86 Hz in the high frequency operation without a problem.

Original language	English
Pages (from-to)	1308-1311
Number of pages	4
Journal	Digest of Technical Papers - SID International Symposium
Volume	42 1
DOIs	https://doi.org/10.1889/1.3621078
Publication status	Published - 2011 Jun

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1889/1.3621078

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abstract = "This thesis deals with the method to improve the gate driver stability of large sized IGZO TFT panel. The proposed Gate driver circuit was designed for 26-inch HD LCD Panel and the circuit has been designed considering the electrical characteristic of instability under the bias stress and temperature This circuit consists of twenty TFT using two clock signals such as CK1,CK2 (Von) and 1 power signals such as VSS (Voff), and new circuit with double inverter suppress the ripple occurrence for every time except actuating time that the signal of the gate line is revealed. By applying the proposed new circuit, the H-SPICE simulation was performed. TFT in integrated circuit can be stable in the low frequency drive (48 Hz) althought δVth was 29 V and It could be applicable to the threshold frequency of 86 Hz in the high frequency operation without a problem.",

author = "Sangjin Jeon and Gwangbum Ko and Jongwoong Chang and Samjin Hwang and Jaemin Myoung",

year = "2011",

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language = "English",

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pages = "1308--1311",

journal = "Digest of Technical Papers - SID International Symposium",

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AU - Jeon, Sangjin

AU - Ko, Gwangbum

AU - Chang, Jongwoong

AU - Hwang, Samjin

AU - Myoung, Jaemin

PY - 2011/6

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N2 - This thesis deals with the method to improve the gate driver stability of large sized IGZO TFT panel. The proposed Gate driver circuit was designed for 26-inch HD LCD Panel and the circuit has been designed considering the electrical characteristic of instability under the bias stress and temperature This circuit consists of twenty TFT using two clock signals such as CK1,CK2 (Von) and 1 power signals such as VSS (Voff), and new circuit with double inverter suppress the ripple occurrence for every time except actuating time that the signal of the gate line is revealed. By applying the proposed new circuit, the H-SPICE simulation was performed. TFT in integrated circuit can be stable in the low frequency drive (48 Hz) althought δVth was 29 V and It could be applicable to the threshold frequency of 86 Hz in the high frequency operation without a problem.

AB - This thesis deals with the method to improve the gate driver stability of large sized IGZO TFT panel. The proposed Gate driver circuit was designed for 26-inch HD LCD Panel and the circuit has been designed considering the electrical characteristic of instability under the bias stress and temperature This circuit consists of twenty TFT using two clock signals such as CK1,CK2 (Von) and 1 power signals such as VSS (Voff), and new circuit with double inverter suppress the ripple occurrence for every time except actuating time that the signal of the gate line is revealed. By applying the proposed new circuit, the H-SPICE simulation was performed. TFT in integrated circuit can be stable in the low frequency drive (48 Hz) althought δVth was 29 V and It could be applicable to the threshold frequency of 86 Hz in the high frequency operation without a problem.

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P-56: Design of gate integrated circuit using IGZO thin film transistors for TFT-LCD panel

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