Optimizing a FPGA-based neural accelerator for small IoT devices

Seongmin Hong; Inho Lee; Yongjun Park

doi:10.23919/ELINFOCOM.2018.8330546

Optimizing a FPGA-based neural accelerator for small IoT devices

Seongmin Hong, Inho Lee, Yongjun Park

College of Computing

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

As neural networks have been widely used for machine-learning algorithms such as image recognition, to design efficient neural accelerators has recently become more important. However, designing neural accelerators is generally difficult because of their high memory storage requirement. In this paper, we propose an area-and-power efficient neural accelerator for small IoT devices, using 4-bit fixed-point weights through quantization technique. The proposed neural accelerator is trained through the TensorFlow infrastructure and the weight data is optimized in order to reduce the overhead of high weight memory requirement. Our FPGA-based design achieves 97.44% accuracy with MNIST 10,000 test images.

Original language	English
Title of host publication	International Conference on Electronics, Information and Communication, ICEIC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-2
Number of pages	2
ISBN (Electronic)	9781538647547
DOIs	https://doi.org/10.23919/ELINFOCOM.2018.8330546
Publication status	Published - 2018 Apr 2
Event	17th International Conference on Electronics, Information and Communication, ICEIC 2018 - Honolulu, United States Duration: 2018 Jan 24 → 2018 Jan 27

Publication series

Name	International Conference on Electronics, Information and Communication, ICEIC 2018
Volume	2018-January

Other

Other	17th International Conference on Electronics, Information and Communication, ICEIC 2018
Country/Territory	United States
City	Honolulu
Period	18/1/24 → 18/1/27

Bibliographical note

Funding Information:
This work was supported in part by the National Research Foundation of Korea (NRF) grants funded by the Korea government (MSIP) (No. NRF- 2015R1C1A1A01053844) and in part by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government(MSIT) (No. 2017-0-00142).

Publisher Copyright:
© 2018 Institute of Electronics and Information Engineers.

All Science Journal Classification (ASJC) codes

Information Systems
Computer Networks and Communications
Computer Science Applications
Signal Processing
Electrical and Electronic Engineering

Access to Document

10.23919/ELINFOCOM.2018.8330546

Cite this

Hong, S., Lee, I., & Park, Y. (2018). Optimizing a FPGA-based neural accelerator for small IoT devices. In International Conference on Electronics, Information and Communication, ICEIC 2018 (pp. 1-2). (International Conference on Electronics, Information and Communication, ICEIC 2018; Vol. 2018-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/ELINFOCOM.2018.8330546

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author = "Seongmin Hong and Inho Lee and Yongjun Park",

note = "Funding Information: This work was supported in part by the National Research Foundation of Korea (NRF) grants funded by the Korea government (MSIP) (No. NRF- 2015R1C1A1A01053844) and in part by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government(MSIT) (No. 2017-0-00142). Publisher Copyright: {\textcopyright} 2018 Institute of Electronics and Information Engineers.; 17th International Conference on Electronics, Information and Communication, ICEIC 2018 ; Conference date: 24-01-2018 Through 27-01-2018",

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Hong, S, Lee, I & Park, Y 2018, Optimizing a FPGA-based neural accelerator for small IoT devices. in International Conference on Electronics, Information and Communication, ICEIC 2018. International Conference on Electronics, Information and Communication, ICEIC 2018, vol. 2018-January, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 17th International Conference on Electronics, Information and Communication, ICEIC 2018, Honolulu, United States, 18/1/24. https://doi.org/10.23919/ELINFOCOM.2018.8330546

Optimizing a FPGA-based neural accelerator for small IoT devices. / Hong, Seongmin; Lee, Inho; Park, Yongjun.
International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-2 (International Conference on Electronics, Information and Communication, ICEIC 2018; Vol. 2018-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Optimizing a FPGA-based neural accelerator for small IoT devices

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