As neural networks have been widely used for machine-learning algorithms such as image recognition, to design efficient neural accelerators has recently become more important. However, designing neural accelerators is generally difficult because of their high memory storage requirement. In this paper, we propose an area-and-power efficient neural accelerator for small IoT devices, using 4-bit fixed-point weights through quantization technique. The proposed neural accelerator is trained through the TensorFlow infrastructure and the weight data is optimized in order to reduce the overhead of high weight memory requirement. Our FPGA-based design achieves 97.44% accuracy with MNIST 10,000 test images.
|Title of host publication||International Conference on Electronics, Information and Communication, ICEIC 2018|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2018 Apr 2|
|Event||17th International Conference on Electronics, Information and Communication, ICEIC 2018 - Honolulu, United States|
Duration: 2018 Jan 24 → 2018 Jan 27
|Name||International Conference on Electronics, Information and Communication, ICEIC 2018|
|Other||17th International Conference on Electronics, Information and Communication, ICEIC 2018|
|Period||18/1/24 → 18/1/27|
Bibliographical noteFunding Information:
This work was supported in part by the National Research Foundation of Korea (NRF) grants funded by the Korea government (MSIP) (No. NRF- 2015R1C1A1A01053844) and in part by Institute for Information & communications Technology Promotion (IITP) grant funded by the Korea government(MSIT) (No. 2017-0-00142).
© 2018 Institute of Electronics and Information Engineers.
All Science Journal Classification (ASJC) codes
- Information Systems
- Computer Networks and Communications
- Computer Science Applications
- Signal Processing
- Electrical and Electronic Engineering