TY - GEN
T1 - Optimization of via structure in multilayer PCB for high speed signal transmission
AU - Kang, Bong Gyu
AU - Kim, Hyun
AU - Kang, Hee Do
AU - Yook, Jong Gwan
PY - 2008
Y1 - 2008
N2 - 44-layers PCB (Printed Circuit Board) for semiconductor test has been analyzed and optimized to improve the transmission performance. By dividing the PCB to subsections and analyzing each section, stub resonance reported in [1] brings the degeneration of transmission performance. To resolve this problem, the blind via can be used, but this technique is not recommended due to high cost and additional process. Hence, this paper proposes that the size of a clearance pad can be optimized to shift the resonance frequency to a higher frequency instead of adopting a blind via. When the size of the clearance pad is optimized, the S21 is improved to about -7 dB in several cases. For the analysis of the entire structure, the PCB is divided into several portions and then, the performance of each portion is analyzed by the 3D full EM simulation. These results are synthesized by circuit simulation. This methodology is verified by comparing between simulation results and measurement results.
AB - 44-layers PCB (Printed Circuit Board) for semiconductor test has been analyzed and optimized to improve the transmission performance. By dividing the PCB to subsections and analyzing each section, stub resonance reported in [1] brings the degeneration of transmission performance. To resolve this problem, the blind via can be used, but this technique is not recommended due to high cost and additional process. Hence, this paper proposes that the size of a clearance pad can be optimized to shift the resonance frequency to a higher frequency instead of adopting a blind via. When the size of the clearance pad is optimized, the S21 is improved to about -7 dB in several cases. For the analysis of the entire structure, the PCB is divided into several portions and then, the performance of each portion is analyzed by the 3D full EM simulation. These results are synthesized by circuit simulation. This methodology is verified by comparing between simulation results and measurement results.
UR - http://www.scopus.com/inward/record.url?scp=60649115092&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=60649115092&partnerID=8YFLogxK
U2 - 10.1109/EDAPS.2008.4736010
DO - 10.1109/EDAPS.2008.4736010
M3 - Conference contribution
AN - SCOPUS:60649115092
SN - 9781424426331
T3 - 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings
SP - 105
EP - 108
BT - 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008 - Proceedings
T2 - 2008 Electrical Design of Advanced Packaging and Systems Symposium, IEEE EDAPS 2008
Y2 - 10 December 2008 through 12 December 2008
ER -