Optimization of self-heating driven leakage current proper-ties of gate-all-around field-effect transistors using neural network modeling and genetic algorithm

Chuntaek Park; Ilgu Yun

doi:10.3390/electronics10212570

Optimization of self-heating driven leakage current proper-ties of gate-all-around field-effect transistors using neural network modeling and genetic algorithm

Chuntaek Park, Ilgu Yun

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

As the technology nodes of semiconductor devices have become finer and more complex, progressive scaling down has been implemented to achieve higher densities for electronic devices. Thus, three-dimensional (3D) channel field-effect transistors (FETs), such as fin-shaped FETs (Fin-FETs) and gate-all-around FETs (GAAFETs), have become popular as they have increased effective surface areas for the channels (Weff), owing to the scaling down strategy. These 3D channel FETs, which have completely covered channel structures with gate oxide and metal, are prone to the self-heating effect (SHE). The SHE is generally known to degrade the on-state drain current; however, when AC pulsed inputs are applied to these devices, the SHE also degrades the off-state leakage current during the off-phase of the pulse. In this study, an optimization methodology to minimize leakage current generation by the SHE is examined.

Original language	English
Article number	2570
Journal	Electronics (Switzerland)
Volume	10
Issue number	21
DOIs	https://doi.org/10.3390/electronics10212570
Publication status	Published - 2021 Nov 1

Bibliographical note

Funding Information:
Funding: This work was supported by the Institute of BioMed-IT, Energy-IT, and Smart-IT Technology (BEST), a Brain Korea 21 plus program at Yonsei University. And The APC was supported by Y-BASE R&E Institute, a Brain Korea 21 four program, Yonsei University.

Funding Information:
Acknowledgments: This work has been supported by Y-BASE R&E Institute, a Brain Korea 21 four program, Yonsei University. The electronic design automation (EDA) tool was also supported by the IC Design Education Center (IDEC), Seoul, Korea.

Publisher Copyright:
© 2021 by the authors. Licensee MDPI, Basel, Switzerland.

All Science Journal Classification (ASJC) codes

Control and Systems Engineering
Signal Processing
Hardware and Architecture
Computer Networks and Communications
Electrical and Electronic Engineering

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10.3390/electronics10212570

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abstract = "As the technology nodes of semiconductor devices have become finer and more complex, progressive scaling down has been implemented to achieve higher densities for electronic devices. Thus, three-dimensional (3D) channel field-effect transistors (FETs), such as fin-shaped FETs (Fin-FETs) and gate-all-around FETs (GAAFETs), have become popular as they have increased effective surface areas for the channels (Weff), owing to the scaling down strategy. These 3D channel FETs, which have completely covered channel structures with gate oxide and metal, are prone to the self-heating effect (SHE). The SHE is generally known to degrade the on-state drain current; however, when AC pulsed inputs are applied to these devices, the SHE also degrades the off-state leakage current during the off-phase of the pulse. In this study, an optimization methodology to minimize leakage current generation by the SHE is examined.",

author = "Chuntaek Park and Ilgu Yun",

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N2 - As the technology nodes of semiconductor devices have become finer and more complex, progressive scaling down has been implemented to achieve higher densities for electronic devices. Thus, three-dimensional (3D) channel field-effect transistors (FETs), such as fin-shaped FETs (Fin-FETs) and gate-all-around FETs (GAAFETs), have become popular as they have increased effective surface areas for the channels (Weff), owing to the scaling down strategy. These 3D channel FETs, which have completely covered channel structures with gate oxide and metal, are prone to the self-heating effect (SHE). The SHE is generally known to degrade the on-state drain current; however, when AC pulsed inputs are applied to these devices, the SHE also degrades the off-state leakage current during the off-phase of the pulse. In this study, an optimization methodology to minimize leakage current generation by the SHE is examined.

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Optimization of self-heating driven leakage current proper-ties of gate-all-around field-effect transistors using neural network modeling and genetic algorithm

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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