Optimization of printed circuit board interconnectivity testing for parallel devices

Research output: Contribution to journalArticlepeer-review


In this article, the problems of test sequence generation and scheduling optimization for a tester with parallel devices are considered in order to reduce inspection times. Two optimization problems are formulated for test sequence generation and the scheduling of parallel devices, and then algorithms to address these problems are proposed. The proposed algorithms were tested via simulation and experiments. The test results show two to four times improvement over existing methods.

Original languageEnglish
Pages (from-to)1750-1760
Number of pages11
JournalEngineering Optimization
Issue number10
Publication statusPublished - 2017 Oct 3

Bibliographical note

Publisher Copyright:
© 2017 Informa UK Limited, trading as Taylor & Francis Group.

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Optimization
  • Management Science and Operations Research
  • Industrial and Manufacturing Engineering
  • Applied Mathematics


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