TY - JOUR
T1 - One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation
AU - Cho, Keonhee
AU - Park, Juhyun
AU - Oh, Tae Woo
AU - Jung, Seong Ook
N1 - Publisher Copyright:
© 2004-2012 IEEE.
PY - 2020/5
Y1 - 2020/5
N2 - This paper presents a one-sided Schmitt-Trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-Trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-Trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-Trigger inverter write assist technique that controls the trip voltage of the Schmitt-Trigger inverter. The proposed Schmitt-Trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang's 10T, the Schmitt-Trigger-based 10T, and MH's 9T static random access memory cells, respectively, based on 22-nm FinFET technology.
AB - This paper presents a one-sided Schmitt-Trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-Trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-Trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-Trigger inverter write assist technique that controls the trip voltage of the Schmitt-Trigger inverter. The proposed Schmitt-Trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang's 10T, the Schmitt-Trigger-based 10T, and MH's 9T static random access memory cells, respectively, based on 22-nm FinFET technology.
KW - Bit interleaving
KW - Schmitt-Trigger
KW - low energy
KW - near-Threshold
KW - static random access memory (SRAM)
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U2 - 10.1109/TCSI.2020.2964903
DO - 10.1109/TCSI.2020.2964903
M3 - Article
AN - SCOPUS:85084405331
SN - 1549-8328
VL - 67
SP - 1551
EP - 1561
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 5
M1 - 9014534
ER -
