Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder

Sungyoul Seo; Hyeonchan Lim; Soyeon Kang; Sungho Kang

doi:10.1109/ISQED.2017.7918315

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder

Sungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20% on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.

Original language	English
Title of host publication	Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017
Publisher	IEEE Computer Society
Pages	191-195
Number of pages	5
ISBN (Electronic)	9781509054046
DOIs	https://doi.org/10.1109/ISQED.2017.7918315
Publication status	Published - 2017 May 2
Event	18th International Symposium on Quality Electronic Design, ISQED 2017 - Santa Clara, United States Duration: 2017 Mar 14 → 2017 Mar 15

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	18th International Symposium on Quality Electronic Design, ISQED 2017
Country/Territory	United States
City	Santa Clara
Period	17/3/14 → 17/3/15

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government(MSIP) (No. 2015R1A2A1A13001751).

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ISQED.2017.7918315

Cite this

Seo, S., Lim, H., Kang, S., & Kang, S. (2017). Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017 (pp. 191-195). [7918315] (Proceedings - International Symposium on Quality Electronic Design, ISQED). IEEE Computer Society. https://doi.org/10.1109/ISQED.2017.7918315

Seo, Sungyoul ; Lim, Hyeonchan ; Kang, Soyeon et al. / Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. pp. 191-195 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

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abstract = "Over recent generations, multi-site testing became the trend in the semiconductor test technology. According to this trend, the solution using low-end automatic test equipment (ATE) and built off self-test (BOST) have been extensively researched in the field of memory test and logic test. Despite the success in the memory test, the logic test still has to solve some problems such as test pin counts, test data volume, etc. In this paper, we present a new off-chip test architecture for improving multi-site testing efficiency, which is composed of tri-state decoders and 3V-level encoders. It is useful to improve total test application time (TAT) by reducing the test pin counts and the test data volume. Moreover, this off-chip is easily compatible with the existing scan compression method. Experimental results show that this test architecture improves the multi-site testing efficiency through reducing TAT by 20% on both International Symposium on Circuits and Systems (ISCAS)'89 and large International Test Conference (ITC)'99 benchmark circuits in all of cases compared to the previous works.",

author = "Sungyoul Seo and Hyeonchan Lim and Soyeon Kang and Sungho Kang",

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Seo, S, Lim, H, Kang, S & Kang, S 2017, Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. in Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017., 7918315, Proceedings - International Symposium on Quality Electronic Design, ISQED, IEEE Computer Society, pp. 191-195, 18th International Symposium on Quality Electronic Design, ISQED 2017, Santa Clara, United States, 17/3/14. https://doi.org/10.1109/ISQED.2017.7918315

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. / Seo, Sungyoul; Lim, Hyeonchan; Kang, Soyeon et al.
Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society, 2017. p. 191-195 7918315 (Proceedings - International Symposium on Quality Electronic Design, ISQED).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Seo S, Lim H, Kang S, Kang S. Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder. In Proceedings of the 18th International Symposium on Quality Electronic Design, ISQED 2017. IEEE Computer Society. 2017. p. 191-195. 7918315. (Proceedings - International Symposium on Quality Electronic Design, ISQED). doi: 10.1109/ISQED.2017.7918315

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder

Abstract

Publication series

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Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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