Non-linear library characterization method for FinFET logic cells by L1-minimization

Byung Su Kim; Hyo Sig Won; Tae Hee Han; Joon Sung Yang

doi:10.1109/ISCAS.2017.8050429

Non-linear library characterization method for FinFET logic cells by L1-minimization

Byung Su Kim, Hyo Sig Won, Tae Hee Han, Joon Sung Yang

College of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

State-of-the-art process technology offers ultra-low power devices operating at ultra-low voltages. However, they show a considerable level of non-linear characteristics. Hence, the accuracy of cell delay and variation modeling for logic cells is expected to be very low with a linear interpolation. In this paper, we propose a compressive sensing based high non-linear cell delay and variation modeling. This paper introduces accuracy optimization methods to fit the delay and variation modeling by pre-processing. Pre-processing is a hybrid approach combining a linear interpolation and compressive sensing for accurate restoration with using less samples. With FinFET cell delay and variation modeling, the experimental results show that the proposed method can obtain a similar or better accuracy with a half of measurement samples than a conventional linear interpolation based modeling.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems
Subtitle of host publication	From Dreams to Innovation, ISCAS 2017 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467368520
DOIs	https://doi.org/10.1109/ISCAS.2017.8050429
Publication status	Published - 2017 Sept 25
Event	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States Duration: 2017 May 28 → 2017 May 31

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
Country/Territory	United States
City	Baltimore
Period	17/5/28 → 17/5/31

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (NRF-2015R1D1A1A01058856) and partially supported by Samsung Research Fund.

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2017.8050429

Cite this

Kim, B. S., Won, H. S., Han, T. H., & Yang, J. S. (2017). Non-linear library characterization method for FinFET logic cells by L1-minimization. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings Article 8050429 (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050429

Kim, Byung Su ; Won, Hyo Sig ; Han, Tae Hee et al. / Non-linear library characterization method for FinFET logic cells by L1-minimization. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. (Proceedings - IEEE International Symposium on Circuits and Systems).

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abstract = "State-of-the-art process technology offers ultra-low power devices operating at ultra-low voltages. However, they show a considerable level of non-linear characteristics. Hence, the accuracy of cell delay and variation modeling for logic cells is expected to be very low with a linear interpolation. In this paper, we propose a compressive sensing based high non-linear cell delay and variation modeling. This paper introduces accuracy optimization methods to fit the delay and variation modeling by pre-processing. Pre-processing is a hybrid approach combining a linear interpolation and compressive sensing for accurate restoration with using less samples. With FinFET cell delay and variation modeling, the experimental results show that the proposed method can obtain a similar or better accuracy with a half of measurement samples than a conventional linear interpolation based modeling.",

author = "Kim, {Byung Su} and Won, {Hyo Sig} and Han, {Tae Hee} and Yang, {Joon Sung}",

note = "Funding Information: ACKNOWLEDGMENT This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (NRF-2015R1D1A1A01058856) and partially supported by Samsung Research Fund. Publisher Copyright: {\textcopyright} 2017 IEEE.; 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",

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Kim, BS, Won, HS, Han, TH & Yang, JS 2017, Non-linear library characterization method for FinFET logic cells by L1-minimization. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050429, Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 17/5/28. https://doi.org/10.1109/ISCAS.2017.8050429

Non-linear library characterization method for FinFET logic cells by L1-minimization. / Kim, Byung Su; Won, Hyo Sig; Han, Tae Hee et al.
IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050429 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: ACKNOWLEDGMENT This research was supported by Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education (NRF-2015R1D1A1A01058856) and partially supported by Samsung Research Fund. Publisher Copyright: © 2017 IEEE.

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Y1 - 2017/9/25

N2 - State-of-the-art process technology offers ultra-low power devices operating at ultra-low voltages. However, they show a considerable level of non-linear characteristics. Hence, the accuracy of cell delay and variation modeling for logic cells is expected to be very low with a linear interpolation. In this paper, we propose a compressive sensing based high non-linear cell delay and variation modeling. This paper introduces accuracy optimization methods to fit the delay and variation modeling by pre-processing. Pre-processing is a hybrid approach combining a linear interpolation and compressive sensing for accurate restoration with using less samples. With FinFET cell delay and variation modeling, the experimental results show that the proposed method can obtain a similar or better accuracy with a half of measurement samples than a conventional linear interpolation based modeling.

AB - State-of-the-art process technology offers ultra-low power devices operating at ultra-low voltages. However, they show a considerable level of non-linear characteristics. Hence, the accuracy of cell delay and variation modeling for logic cells is expected to be very low with a linear interpolation. In this paper, we propose a compressive sensing based high non-linear cell delay and variation modeling. This paper introduces accuracy optimization methods to fit the delay and variation modeling by pre-processing. Pre-processing is a hybrid approach combining a linear interpolation and compressive sensing for accurate restoration with using less samples. With FinFET cell delay and variation modeling, the experimental results show that the proposed method can obtain a similar or better accuracy with a half of measurement samples than a conventional linear interpolation based modeling.

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Kim BS, Won HS, Han TH, Yang JS. Non-linear library characterization method for FinFET logic cells by L1-minimization. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050429. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS.2017.8050429

Non-linear library characterization method for FinFET logic cells by L1-minimization

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