Noise constrained power optimization for dual V_T domino logic

In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. Specially, when dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic node much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.