TY - GEN
T1 - Noise constrained power optimization for dual V/sub T/ domino logic
AU - Jung, Seong Ook
AU - Kim, Ki Wook
AU - Kang, Sung Mo
PY - 2001
Y1 - 2001
N2 - In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
AB - In dual threshold voltage techniques, significant subthreshold leakage current is one of the most important design problems. When dual threshold voltage is applied to the domino logic, noise immunity has to be carefully considered because the significant subthreshold current makes dynamic nodes much more susceptible to noise. In this paper, an analytical model for proper keeper transistor sizing to meet noise constraint is presented. Based on the same noise constraint, we propose dual threshold voltage domino logic technique to save power consumption.
UR - http://www.scopus.com/inward/record.url?scp=2942652744&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=2942652744&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.922196
DO - 10.1109/ISCAS.2001.922196
M3 - Conference contribution
AN - SCOPUS:2942652744
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 158
EP - 161
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -