NiO resistive random access memory nanocapacitor array on graphene

In this study, a NiO RRAM nanocapacitor array was fabricated on a graphene sheet, which was on a Nb-doped SrTiO₃ substrate containing terraces with a regular interval of about 100 nm and an atomically smooth surface. For the formation of the NiO RRAM nanocapacitor (Pt/NiO/graphene capacitor) array, an anodic aluminum oxide (AAO) nanotemplate with a pore diameter of about 30 nm and an interpore distance of about 100 nm was used. NiO and Pt were subsequently deposited on the graphene sheet. The NiO RRAM nanocapacitor had a diameter of about 30 ± 2 nm and a thickness of about 33 ± 3 nm. Typical unipolar switching characteristics of the NiO RRAM nanocapacitor array were confirmed. The NiO RRAM nanocapacitor array on graphene exhibited lower SET and RESET voltages than that on a bare surface of Nb-doped SrTiO₃.