Multi-operation-based constrained random verification for on-chip memory

Hyeonuk Son, Jaewon Jang, Heetae Kim, Sungho Kang

Research output: Contribution to journalArticlepeer-review


Current verification methods for on-chip memory have been implemented using coverpoints that are generated based on a single operation. These coverpoints cannot consider the influence of other memory banks in a busy state. In this paper, we propose a method in which the coverpoints account for all operations executed on different memory banks. In addition, a new constrained random vector generation method is proposed to reduce the required random vectors for the multi-operation-based coverpoints. The simulation results on NAND flash memory show 100% coverage with 496,541 constrained random vectors indicating a reduction of 96.4% compared with conventional random vectors. Index Terms—Constrained random verification (CRV), functional verification, coverpoint, NAND flash, constrained random vectors.

Original languageEnglish
Pages (from-to)423-426
Number of pages4
JournalJournal of Semiconductor Technology and Science
Issue number3
Publication statusPublished - 2015 Jun 1

Bibliographical note

Publisher Copyright:
© 2015, Institute of Electronics Engineers of Korea. All rights reserved.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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