MTJ based non-volatile flip-flop in deep submicron technology

Youngdon Jung; Jisu Kim; Kyungho Ryu; Scong Ook Jung; Jung Pill Kim; Seung H. Kang

doi:10.1109/isocc.2011.6138622

MTJ based non-volatile flip-flop in deep submicron technology

Youngdon Jung, Jisu Kim, Kyungho Ryu, Scong Ook Jung, Jung Pill Kim, Seung H. Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Citations (Scopus)

Abstract

The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

Original language	English
Title of host publication	2011 International SoC Design Conference, ISOCC 2011
Publisher	IEEE Computer Society
Pages	424-427
Number of pages	4
ISBN (Print)	9781457707100
DOIs	https://doi.org/10.1109/isocc.2011.6138622
Publication status	Published - 2011
Event	8th International SoC Design Conference 2011, ISOCC 2011 - Jeju, Korea, Republic of Duration: 2011 Nov 17 → 2011 Nov 18

Publication series

Name	2011 International SoC Design Conference, ISOCC 2011

Other

Other	8th International SoC Design Conference 2011, ISOCC 2011
Country/Territory	Korea, Republic of
City	Jeju
Period	11/11/17 → 11/11/18

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/isocc.2011.6138622

Cite this

@inproceedings{6651ab50809546baad4a00b5d66eb8e8,

title = "MTJ based non-volatile flip-flop in deep submicron technology",

abstract = "The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.",

author = "Youngdon Jung and Jisu Kim and Kyungho Ryu and Jung, {Scong Ook} and Kim, {Jung Pill} and Kang, {Seung H.}",

year = "2011",

doi = "10.1109/isocc.2011.6138622",

language = "English",

isbn = "9781457707100",

series = "2011 International SoC Design Conference, ISOCC 2011",

publisher = "IEEE Computer Society",

pages = "424--427",

booktitle = "2011 International SoC Design Conference, ISOCC 2011",

address = "United States",

note = "8th International SoC Design Conference 2011, ISOCC 2011 ; Conference date: 17-11-2011 Through 18-11-2011",

}

Jung, Y, Kim, J, Ryu, K, Jung, SO, Kim, JP & Kang, SH 2011, MTJ based non-volatile flip-flop in deep submicron technology. in 2011 International SoC Design Conference, ISOCC 2011. 2011 International SoC Design Conference, ISOCC 2011, IEEE Computer Society, pp. 424-427, 8th International SoC Design Conference 2011, ISOCC 2011, Jeju, Korea, Republic of, 11/11/17. https://doi.org/10.1109/isocc.2011.6138622

TY - GEN

T1 - MTJ based non-volatile flip-flop in deep submicron technology

AU - Jung, Youngdon

AU - Kim, Jisu

AU - Ryu, Kyungho

AU - Jung, Scong Ook

AU - Kim, Jung Pill

AU - Kang, Seung H.

PY - 2011

Y1 - 2011

N2 - The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

AB - The NVFF (Non-Volatile Flip-flop) using a MTJ is one of the powerful solutions for the low power system. However, the previous NVFF cannot provide a sufficient current to write the data into the MTJ in deep submicron technology. This problem occurs due to the lowered supply voltage (1.1V for core device in 45nm technolog) with technology scaling. It can be resolved by increasing the supply voltage. However, the increased supply voltage causes a reliability problem of the core device. In order to overcome this problem, the proposed write circuit adopts an IO device with an IO supply voltage of 1.8V. In addition, the low-skewed NAND (LS-NAND) is used to efficiently interface the two supply voltage levels of 1.1V and 1.8V and to minimize the short circuit current in the write circuit. In this paper, the NVFF with the proposed write circuit is verified by HSPICE simulation using an industry compatible 45nm model parameter. The write current of the proposed write circuit is 60% greater than that of the previous write circuit and is sufficient for the proper write operation.

UR - http://www.scopus.com/inward/record.url?scp=84863127302&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84863127302&partnerID=8YFLogxK

U2 - 10.1109/isocc.2011.6138622

DO - 10.1109/isocc.2011.6138622

M3 - Conference contribution

AN - SCOPUS:84863127302

SN - 9781457707100

T3 - 2011 International SoC Design Conference, ISOCC 2011

SP - 424

EP - 427

BT - 2011 International SoC Design Conference, ISOCC 2011

PB - IEEE Computer Society

T2 - 8th International SoC Design Conference 2011, ISOCC 2011

Y2 - 17 November 2011 through 18 November 2011

ER -

MTJ based non-volatile flip-flop in deep submicron technology

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