Memory-efficient and high-speed LDPC encoder

Y. Jung, Y. Jung, J. Kim

Research output: Contribution to journalArticlepeer-review

11 Citations (Scopus)


A memory-efficient and high-speed low-density parity-check (LDPC) encoder is proposed, which uses a memory efficient parity-check matrix, called a differential parity-check matrix. The partially parallel architecture is also proposed for use in high-speed encoding. The proposed two-stage cyclic shifter is appropriate for a differential parity-check matrix and partially parallel architecture with low complexity. The proposed LDPC encoder is implemented with a 21 reduction in memory. The speed of the proposed partially parallel LDPC encoder is three times faster than the existing serial LDPC encoder.

Original languageEnglish
Pages (from-to)1035-1036
Number of pages2
JournalElectronics Letters
Issue number14
Publication statusPublished - 2010 Jul 8

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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