Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

Jeff Huang; Paul D. Kirsch; Jungwoo Oh; Se Hoon Lee; Prashant Majhi; H. Rusty Harris; Daivd C. Gilmer; Gennadi Bersuker; Dawei Heh; Chang Seo Park; Chanro Park; Hsing Huang Tseng; Raj Jammy

doi:10.1109/LED.2008.2011754

Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

Jeff Huang, Paul D. Kirsch, Jungwoo Oh, Se Hoon Lee, Prashant Majhi, H. Rusty Harris, Daivd C. Gilmer, Gennadi Bersuker, Dawei Heh, Chang Seo Park, Chanro Park, Hsing Huang Tseng, Raj Jammy

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

21 Citations (Scopus)

Abstract

This letter addresses mechanisms responsible for a high gate leakage current J_g) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiO_x interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high J_g. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with J_g comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

Original language	English
Pages (from-to)	285-287
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	30
Issue number	3
DOIs	https://doi.org/10.1109/LED.2008.2011754
Publication status	Published - 2009

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2008.2011754

Cite this

@article{b33efdad534b408793fd8d47a60eb0ee,

title = "Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe",

abstract = "This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.",

author = "Jeff Huang and Kirsch, {Paul D.} and Jungwoo Oh and Lee, {Se Hoon} and Prashant Majhi and Harris, {H. Rusty} and Gilmer, {Daivd C.} and Gennadi Bersuker and Dawei Heh and Park, {Chang Seo} and Chanro Park and Tseng, {Hsing Huang} and Raj Jammy",

year = "2009",

doi = "10.1109/LED.2008.2011754",

language = "English",

volume = "30",

pages = "285--287",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "3",

}

TY - JOUR

T1 - Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

AU - Huang, Jeff

AU - Kirsch, Paul D.

AU - Oh, Jungwoo

AU - Lee, Se Hoon

AU - Majhi, Prashant

AU - Harris, H. Rusty

AU - Gilmer, Daivd C.

AU - Bersuker, Gennadi

AU - Heh, Dawei

AU - Park, Chang Seo

AU - Park, Chanro

AU - Tseng, Hsing Huang

AU - Jammy, Raj

PY - 2009

Y1 - 2009

N2 - This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

AB - This letter addresses mechanisms responsible for a high gate leakage current Jg) and a thick interfacial layer in the surface channel SiGe pFET enabling transistor fabrication with sub-1-nm equivalent-oxide-thickness (EOT) high-k/metal gate stack. The primary mechanism limiting EOT scaling is Ge-enhanced Si oxidation resulting in a thick (1.4-nm) SiOx interface layer. A secondary mechanism, i.e., Ge diffusion (>3%) into high-k, results in high Jg. In the framework of this understanding, we optimized a high-k nitridation process to form as an efficient diffusion barrier, which reduces both O and Ge diffusion resulting in the total gate stack EOT ∼0.9 nm with Jg comparable to that of bulk Si substrate samples. The proposed plasma nitridation process enables fabrication of the sub-1-nm EOT gate-first gate stack with HfSiON dielectric directly on SiGe without Si cap.

UR - http://www.scopus.com/inward/record.url?scp=62549137369&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62549137369&partnerID=8YFLogxK

U2 - 10.1109/LED.2008.2011754

DO - 10.1109/LED.2008.2011754

M3 - Article

AN - SCOPUS:62549137369

SN - 0741-3106

VL - 30

SP - 285

EP - 287

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 3

ER -

Mechanisms limiting EOT scaling and gate leakage currents of high-k/ Metal gate stacks directly on SiGe

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this