MDSI: Signal integrity interconnect fault modeling and testing for SoCs

Sunghoon Chun; Yongjoon Kim; Sungho Kang

doi:10.1007/s10836-006-0630-0

MDSI: Signal integrity interconnect fault modeling and testing for SoCs

Sunghoon Chun, Yongjoon Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

21 Citations (Scopus)

Abstract

Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

Original language	English
Pages (from-to)	357-362
Number of pages	6
Journal	Journal of Electronic Testing: Theory and Applications (JETTA)
Volume	23
Issue number	4
DOIs	https://doi.org/10.1007/s10836-006-0630-0
Publication status	Published - 2007 Aug

Bibliographical note

Funding Information:
This work was supported by the Korea Science and Engineering Foundation Grant funded by the Korea government (MOST) No. R01-2006-000-11038-0.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1007/s10836-006-0630-0

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AB - Unacceptable loss of signal integrity may cause permanent or intermittent harm to the functionality and performance of SoCs. In this paper, we present an abstract model and a new test pattern generation method of signal integrity problems on interconnects. This approach is achieved by considering the effects for testing inputs and parasitic RLC elements of interconnects. We also develop a framework to deal with arbitrary interconnection topology. Experimental results show that the proposed signal integrity fault model is more exact and more powerful for long interconnects than previous approaches.

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MDSI: Signal integrity interconnect fault modeling and testing for SoCs

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

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