Marker layout for optimizing the overlay alignment in a photolithography process

Ki Bum Lee, Chang Ouk Kim

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


In the photolithography process of wafer fabrication, a mask pattern is transferred to a wafer in a layer-by-layer fashion, and the pattern alignment of adjacent layers is critical to the wafer yield. To enhance the alignment precision, an overlay metrology system measures the overlay error at some markers on the wafer, and the error information is used for constructing an overlay correction model. During the overlay alignment, the layout of the markers has a significant impact on the correction of the overlay error. After the maximum number of available markers has been determined based on the quality and turn-around time of the target device, the positions of those markers should be determined in such a way that the overlay error correction model shows robust performance for future wafers. In this paper, we propose a sparse particle swarm optimization algorithm to find an optimal marker layout in terms of robust performance characterized by the overlay error prediction and irregularity of marker positions. In the experiment, the performance of the marker layouts suggested by several search algorithms was tested on three different layers, and the proposed algorithm demonstrated superiority over the other algorithms.

Original languageEnglish
Article number8675528
Pages (from-to)212-219
Number of pages8
JournalIEEE Transactions on Semiconductor Manufacturing
Issue number2
Publication statusPublished - 2019 May

Bibliographical note

Funding Information:
Manuscript received January 28, 2019; revised March 15, 2019; accepted March 24, 2019. Date of publication March 27, 2019; date of current version May 3, 2019. This work was supported in part by the National Research Foundation of Korea (NRF) grant funded by the Ministry of Education (Global Ph.D. Fellowship Program) under Grant NRF-2015H1A2A1031081, in part by NRF grant funded by the Ministry of Science and ICT under Grant NRF-2016R1A2B4008337, in part by the Graduate School of Yonsei University Research Scholarship Grants in 2018, and in part by SK Hynix Company Ltd. (Corresponding author: Chang Ouk Kim.) The authors are with the Department of Industrial Engineering, Yonsei University, Seoul 03722, South Korea (e-mail:

Publisher Copyright:
© 1988-2012 IEEE.

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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