Low-voltage, high-speed circuit designs for gigabit DRAM's

Kyuchan Lee; Changhyun Kim; Dong Ryul Ryu; Jai Hoon Sim; Sang Bo Lee; Byung Sik Moon; Keum Yong Kim; Nam Jong Kim; Seung Moon Yoo; Hongil Yoon; Jei Hwan Yoo; Soo In Cho

doi:10.1109/4.568824

Low-voltage, high-speed circuit designs for gigabit DRAM's

Kyuchan Lee, Changhyun Kim, Dong Ryul Ryu, Jai Hoon Sim, Sang Bo Lee, Byung Sik Moon, Keum Yong Kim, Nam Jong Kim, Seung Moon Yoo, Hongil Yoon, Jei Hwan Yoo, Soo In Cho

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

16 Citations (Scopus)

Abstract

This paper describes several new circuit design techniques for low V _CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV _BL) as well as the V _GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t _RAC) of 28 ns at V _CC = 1.5 V and T = 25°C has been obtained.

Original language	English
Pages (from-to)	642-647
Number of pages	6
Journal	IEEE Journal of Solid-State Circuits
Volume	32
Issue number	5
DOIs	https://doi.org/10.1109/4.568824
Publication status	Published - 1997 May

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/4.568824

Cite this

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title = "Low-voltage, high-speed circuit designs for gigabit DRAM's",

abstract = "This paper describes several new circuit design techniques for low V CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV BL) as well as the V GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t RAC) of 28 ns at V CC = 1.5 V and T = 25°C has been obtained.",

keywords = "Current sense amplifier, Dynamic random access memory, Gigabit, High-speed integrated circuits, Low-voltage integrated circuits",

author = "Kyuchan Lee and Changhyun Kim and Ryu, {Dong Ryul} and Sim, {Jai Hoon} and Lee, {Sang Bo} and Moon, {Byung Sik} and Kim, {Keum Yong} and Kim, {Nam Jong} and Yoo, {Seung Moon} and Hongil Yoon and Yoo, {Jei Hwan} and Cho, {Soo In}",

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T1 - Low-voltage, high-speed circuit designs for gigabit DRAM's

AU - Lee, Kyuchan

AU - Kim, Changhyun

AU - Ryu, Dong Ryul

AU - Sim, Jai Hoon

AU - Lee, Sang Bo

AU - Moon, Byung Sik

AU - Kim, Keum Yong

AU - Kim, Nam Jong

AU - Yoo, Seung Moon

AU - Yoon, Hongil

AU - Yoo, Jei Hwan

AU - Cho, Soo In

PY - 1997/5

Y1 - 1997/5

N2 - This paper describes several new circuit design techniques for low V CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV BL) as well as the V GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t RAC) of 28 ns at V CC = 1.5 V and T = 25°C has been obtained.

AB - This paper describes several new circuit design techniques for low V CC regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (ΔV BL) as well as the V GS margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a high gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-μm twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t RAC) of 28 ns at V CC = 1.5 V and T = 25°C has been obtained.

KW - Current sense amplifier

KW - Dynamic random access memory

KW - Gigabit

KW - High-speed integrated circuits

KW - Low-voltage integrated circuits

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Low-voltage, high-speed circuit designs for gigabit DRAM's

Abstract

All Science Journal Classification (ASJC) codes

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