Low-swing clock domino logic incorporating dual supply and dual threshold voltages

Seong Ook Jung, Ki Wook Kim, Sung Mo Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)


High-speed domino logic is now prevailing in performance critical block of a chip. Low Voltage Swing Clock (LVSC) domino logic family is developed for substantial dynamic power saving. To boost up the transition speed in proposed circuitry, a well-established dual threshold voltage technique is exploited. Dual supply voltage technique in the LVSC domino logic is geared to reduce power consumption in clock tree and logic gates effectively. Delay Constrained Power Optimization (DCPO) algorithm allocates low supply voltage to logic gates such that dynamic power consumed by logic gates is minimized. Delay time variations due to gate-to-source voltage change and and input signal arrival time difference are considered for accurate timing analysis in DCPO.

Original languageEnglish
Title of host publicationProceedings of the 39th Annual Design Automation Conference, DAC'02
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)1581134614
Publication statusPublished - 2002
Event39th Design Automation Conference - New Orleans, LA, United States
Duration: 2002 Jun 102002 Jun 14

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Conference39th Design Automation Conference
Country/TerritoryUnited States
CityNew Orleans, LA

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering


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