Low Power Scan Chain Architecture Based on Circuit Topology

Heetae Kim; Hyunggoy Oh; Sangjun Lee; Sungho Kang

doi:10.1109/ISOCC.2018.8649956

Low Power Scan Chain Architecture Based on Circuit Topology

Heetae Kim, Hyunggoy Oh, Sangjun Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2018, ISOCC 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	267-268
Number of pages	2
ISBN (Electronic)	9781538679609
DOIs	https://doi.org/10.1109/ISOCC.2018.8649956
Publication status	Published - 2019 Feb 22
Event	15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of Duration: 2018 Nov 12 → 2018 Nov 15

Publication series

Name	Proceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference	15th International SoC Design Conference, ISOCC 2018
Country/Territory	Korea, Republic of
City	Daegu
Period	18/11/12 → 18/11/15

Bibliographical note

Funding Information:
ACKNOWLEDGMENT This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].

Publisher Copyright:
© 2018 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2018.8649956

Cite this

Kim, H., Oh, H., Lee, S., & Kang, S. (2019). Low Power Scan Chain Architecture Based on Circuit Topology. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 267-268). Article 8649956 (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649956

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abstract = "Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.",

author = "Heetae Kim and Hyunggoy Oh and Sangjun Lee and Sungho Kang",

note = "Funding Information: ACKNOWLEDGMENT This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC]. Publisher Copyright: {\textcopyright} 2018 IEEE.; 15th International SoC Design Conference, ISOCC 2018 ; Conference date: 12-11-2018 Through 15-11-2018",

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language = "English",

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Kim, H, Oh, H, Lee, S & Kang, S 2019, Low Power Scan Chain Architecture Based on Circuit Topology. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649956, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 267-268, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 18/11/12. https://doi.org/10.1109/ISOCC.2018.8649956

Low Power Scan Chain Architecture Based on Circuit Topology. / Kim, Heetae; Oh, Hyunggoy; Lee, Sangjun et al.
Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 267-268 8649956 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Low Power Scan Chain Architecture Based on Circuit Topology

AU - Kim, Heetae

AU - Oh, Hyunggoy

AU - Lee, Sangjun

AU - Kang, Sungho

N1 - Funding Information: ACKNOWLEDGMENT This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC]. Publisher Copyright: © 2018 IEEE.

PY - 2019/2/22

Y1 - 2019/2/22

N2 - Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.

AB - Scan-based test is widely used method to test the digital circuits, increasing the controllability of the circuit under test. However high controllability can cause fatal problems by excessive test power consumption. To resolve these problem, this paper proposes a scan chain architecture which reduces the test power consumption. The proposed method decreases the test data volume by partitioning a scan chain into many scan segments. The scan chain partitioning is performed based on circuit topology, and it increases the number of scan segments that can be bypassed. Simulation results show that the proposed method reduces the test power consumption up to 43.33% compared to the previous work.

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ER -

Low Power Scan Chain Architecture Based on Circuit Topology

Abstract

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All Science Journal Classification (ASJC) codes

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