Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA

Kyungseon Cho; Seungjin Lee; Choongkeun Lee; Taegun Yim; Hongil Yoon

doi:10.1109/ISOCC.2017.8368792

Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA

Kyungseon Cho, Seungjin Lee, Choongkeun Lee, Taegun Yim, Hongil Yoon

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

The conventional magnetic RAM (MRAM) LUTs for non-volatile field programmable gate arrays (FPGA) have excellent overall power characteristics for read and static modes but sufficient reliability of data operation has not been met due to the large process variations in the cell process technology. The novel MRAM LUT proposed in this paper can serve to enhance the reliability, reduce the power significantly and reduce implementation size by structuring multi-context in a single MRAM LUT. In an efficient manner, based on the output transition rate of 15%, the proposed 6-input MRAM LUT with 8-context shows 49.6% smaller power consumption and 18.1% smaller area compared to those of the 8 6-input SRAM LUTs.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	107-108
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368792
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368792

Cite this

Cho, K., Lee, S., Lee, C., Yim, T., & Yoon, H. (2018). Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 107-108). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368792

Cho, Kyungseon ; Lee, Seungjin ; Lee, Choongkeun et al. / Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA. Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 107-108 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

@inproceedings{3dfd0e9058884cf6982cef14df3f729f,

title = "Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA",

abstract = "The conventional magnetic RAM (MRAM) LUTs for non-volatile field programmable gate arrays (FPGA) have excellent overall power characteristics for read and static modes but sufficient reliability of data operation has not been met due to the large process variations in the cell process technology. The novel MRAM LUT proposed in this paper can serve to enhance the reliability, reduce the power significantly and reduce implementation size by structuring multi-context in a single MRAM LUT. In an efficient manner, based on the output transition rate of 15%, the proposed 6-input MRAM LUT with 8-context shows 49.6% smaller power consumption and 18.1% smaller area compared to those of the 8 6-input SRAM LUTs.",

keywords = "Look-up table, Non-volatile FPGA, STT-MRAM",

author = "Kyungseon Cho and Seungjin Lee and Choongkeun Lee and Taegun Yim and Hongil Yoon",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

month = may,

day = "29",

doi = "10.1109/ISOCC.2017.8368792",

language = "English",

series = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "107--108",

booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

address = "United States",

}

Cho, K, Lee, S, Lee, C, Yim, T & Yoon, H 2018, Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 107-108, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368792

Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA. / Cho, Kyungseon; Lee, Seungjin; Lee, Choongkeun et al.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 107-108 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA

AU - Cho, Kyungseon

AU - Lee, Seungjin

AU - Lee, Choongkeun

AU - Yim, Taegun

AU - Yoon, Hongil

PY - 2018/5/29

Y1 - 2018/5/29

N2 - The conventional magnetic RAM (MRAM) LUTs for non-volatile field programmable gate arrays (FPGA) have excellent overall power characteristics for read and static modes but sufficient reliability of data operation has not been met due to the large process variations in the cell process technology. The novel MRAM LUT proposed in this paper can serve to enhance the reliability, reduce the power significantly and reduce implementation size by structuring multi-context in a single MRAM LUT. In an efficient manner, based on the output transition rate of 15%, the proposed 6-input MRAM LUT with 8-context shows 49.6% smaller power consumption and 18.1% smaller area compared to those of the 8 6-input SRAM LUTs.

AB - The conventional magnetic RAM (MRAM) LUTs for non-volatile field programmable gate arrays (FPGA) have excellent overall power characteristics for read and static modes but sufficient reliability of data operation has not been met due to the large process variations in the cell process technology. The novel MRAM LUT proposed in this paper can serve to enhance the reliability, reduce the power significantly and reduce implementation size by structuring multi-context in a single MRAM LUT. In an efficient manner, based on the output transition rate of 15%, the proposed 6-input MRAM LUT with 8-context shows 49.6% smaller power consumption and 18.1% smaller area compared to those of the 8 6-input SRAM LUTs.

KW - Look-up table

KW - Non-volatile FPGA

KW - STT-MRAM

UR - http://www.scopus.com/inward/record.url?scp=85048873354&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85048873354&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2017.8368792

DO - 10.1109/ISOCC.2017.8368792

M3 - Conference contribution

AN - SCOPUS:85048873354

T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017

SP - 107

EP - 108

BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 14th International SoC Design Conference, ISOCC 2017

Y2 - 5 November 2017 through 8 November 2017

ER -

Cho K, Lee S, Lee C, Yim T, Yoon H. Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA. In Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 107-108. (Proceedings - International SoC Design Conference 2017, ISOCC 2017). doi: 10.1109/ISOCC.2017.8368792

Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

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