Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs

Junha Im; Misuk Cho; Yunho Jung; Jaeseok Kim

doi:10.1109/ISCAS.2009.5117820

Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs

Junha Im, Misuk Cho, Yunho Jung, Jaeseok Kim

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-μm CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130Mbps. The logic gate count for the processor is 978K and the power consumption is 62 / 284mW (TX / RX), respectively.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	601-604
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5117820
Publication status	Published - 2009
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan, Province of China Duration: 2009 May 24 → 2009 May 27

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Other

Other	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan, Province of China
City	Taipei
Period	09/5/24 → 09/5/27

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2009.5117820

Cite this

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title = "Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs",

abstract = "In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-μm CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130Mbps. The logic gate count for the processor is 978K and the power consumption is 62 / 284mW (TX / RX), respectively.",

author = "Junha Im and Misuk Cho and Yunho Jung and Jaeseok Kim",

year = "2009",

doi = "10.1109/ISCAS.2009.5117820",

language = "English",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "601--604",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

}

Im, J, Cho, M, Jung, Y & Kim, J 2009, Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5117820, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 601-604, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, Province of China, 09/5/24. https://doi.org/10.1109/ISCAS.2009.5117820

Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs. / Im, Junha; Cho, Misuk; Jung, Yunho et al.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 601-604 5117820 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

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N2 - In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-μm CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130Mbps. The logic gate count for the processor is 978K and the power consumption is 62 / 284mW (TX / RX), respectively.

AB - In this paper, we propose an efficient design and implementation results of a high speed 2TX-2RX multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor includes bit-parallel processing transmitter physical layer convergence procedure (TX-PLCP) processor and space-division multiplexing (SDM) symbol detector, which have been optimized for low power consumption and low hardware overhead. It was implemented using 0.18-μm CMOS technology. The proposed architecture can operate at a 40-MHz clock frequency and supports the maximum data rate of 130Mbps. The logic gate count for the processor is 978K and the power consumption is 62 / 284mW (TX / RX), respectively.

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BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

Y2 - 24 May 2009 through 27 May 2009

ER -

Low-power low-complexity MIMO-OFDM baseband processor for wireless LANs

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