Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

Seung Moon Yoo; Seong Ook Jung; Sung Mo Kang

doi:10.1109/ISCAS.2001.922153

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

Seung Moon Yoo, Seong Ook Jung, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

In this paper, a new test pattern generator with a 2-level LFSR and a fast pattern transferring method for the scan-based BIST structure are proposed. XOR input paths in the 2-level LFSR scheme are changed by counter outputs to generate less linear-dependent and auto-correlated test patterns for better fault coverage. Test patterns are transferred into the scan chain by using an asynchronous internal high frequency clock to reduce test time.

Original language	English
Title of host publication	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages	1-4
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2001.922153
Publication status	Published - 2001
Event	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia Duration: 2001 May 6 → 2001 May 9

Publication series

Name	ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume	4

Other

Other	2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Country/Territory	Australia
City	Sydney, NSW
Period	01/5/6 → 01/5/9

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS.2001.922153

Cite this

Yoo, S. M., Jung, S. O., & Kang, S. M. (2001). Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. In ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings (pp. 1-4). Article 922153 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4). https://doi.org/10.1109/ISCAS.2001.922153

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title = "Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT",

abstract = "In this paper, a new test pattern generator with a 2-level LFSR and a fast pattern transferring method for the scan-based BIST structure are proposed. XOR input paths in the 2-level LFSR scheme are changed by counter outputs to generate less linear-dependent and auto-correlated test patterns for better fault coverage. Test patterns are transferred into the scan chain by using an asynchronous internal high frequency clock to reduce test time.",

author = "Yoo, {Seung Moon} and Jung, {Seong Ook} and Kang, {Sung Mo}",

year = "2001",

doi = "10.1109/ISCAS.2001.922153",

language = "English",

isbn = "0780366859",

series = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

pages = "1--4",

booktitle = "ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings",

note = "2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 ; Conference date: 06-05-2001 Through 09-05-2001",

}

Yoo, SM, Jung, SO & Kang, SM 2001, Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. in ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings., 922153, ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings, vol. 4, pp. 1-4, 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, Sydney, NSW, Australia, 01/5/6. https://doi.org/10.1109/ISCAS.2001.922153

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. / Yoo, Seung Moon; Jung, Seong Ook; Kang, Sung Mo.
ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings. 2001. p. 1-4 922153 (ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings; Vol. 4).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Jung, Seong Ook

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PY - 2001

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N2 - In this paper, a new test pattern generator with a 2-level LFSR and a fast pattern transferring method for the scan-based BIST structure are proposed. XOR input paths in the 2-level LFSR scheme are changed by counter outputs to generate less linear-dependent and auto-correlated test patterns for better fault coverage. Test patterns are transferred into the scan chain by using an asynchronous internal high frequency clock to reduce test time.

AB - In this paper, a new test pattern generator with a 2-level LFSR and a fast pattern transferring method for the scan-based BIST structure are proposed. XOR input paths in the 2-level LFSR scheme are changed by counter outputs to generate less linear-dependent and auto-correlated test patterns for better fault coverage. Test patterns are transferred into the scan chain by using an asynchronous internal high frequency clock to reduce test time.

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BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

Y2 - 6 May 2001 through 9 May 2001

ER -

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT

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