Abstract
Lock elision is a technique to replace coarse-grained locks by optimistic concurrent execution. In this paper, we introduce lock elision for protected objects (POs) in Ada. We employ Intel Transactional Synchronization Extensions (TSX) as the underlying hardware transactional memory facility. With TSX, a processor can detect dynamically whether tasks need to serialize through critical sections protected by locks. We adapt the GNU Ada run-time library (GNARL) to elide locks transparently from protected functions and procedures. We critically evaluate opportunities and difficulties of lock elision with protected entries. We demonstrate that lock elision can achieve significant performance improvements for a selection of three synthetic and one real-world benchmark. We show the scalability of our approach for up to 44 cores of a two-CPU, 44-core Intel E5-2699 v4 system.
Original language | English |
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Title of host publication | Reliable Software Technologies - Ada-Europe 2017 - 22nd Ada-Europe International Conference on Reliable Software Technologies, Proceedings |
Editors | Markus Bader, Johann Blieberger |
Publisher | Springer Verlag |
Pages | 121-136 |
Number of pages | 16 |
ISBN (Print) | 9783319605876 |
DOIs | |
Publication status | Published - 2017 |
Event | 22nd International Conference on Reliable Software Technologies, Ada-Europe 2017 - Vienna, Austria Duration: 2017 Jun 12 → 2017 Jun 16 |
Publication series
Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
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Volume | 10300 LNCS |
ISSN (Print) | 0302-9743 |
ISSN (Electronic) | 1611-3349 |
Other
Other | 22nd International Conference on Reliable Software Technologies, Ada-Europe 2017 |
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Country/Territory | Austria |
City | Vienna |
Period | 17/6/12 → 17/6/16 |
Bibliographical note
Funding Information:Research supported by the Next-Generation Information Computing Development Program through the National Research Foundation of Korea (NRF), funded by the Ministry of Science, ICT & Future Planning under grant NRF2015M3C4A7065522.
Publisher Copyright:
© Springer International Publishing AG 2017.
All Science Journal Classification (ASJC) codes
- Theoretical Computer Science
- Computer Science(all)