LL-PCM: Low-latency phase change memory architecture

Nam Sung Kim; Choungki Song; Woo Young Cho; Jian Huang; Myoungsoo Jung

doi:10.1145/3316781.3317853

LL-PCM: Low-latency phase change memory architecture

Nam Sung Kim, Choungki Song, Woo Young Cho, Jian Huang, Myoungsoo Jung

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can significantly degrade system performance. In this paper, we analyze a PCM implementation in depth, and identify the primary cause of PCM's long latency, i.e., a long interconnect (high resistance/capacitance) path between a cell and a sense-amp/writedriver. This in turn requires (1) a very large charge pump consuming: ∼20% of PCM chip space, ∼50% of latency of write operations, and ∼2× more power than a write operation itself; and (2) a large current sense-amp with long time to pre-charge the interconnect path. Then, we propose Low-Latency PCM (LLPCM) architecture. Our analysis shows that LL-PCM can give 119% higher performance and consume 43% lower memory energy than PCM for memory-intensive applications. LL-PCM is only ∼1% larger than PCM, as the cost of reducing the resistance/capacitance of the interconnect path is negated by its 4.1× smaller charge pump.

Original language	English
Title of host publication	Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450367257
DOIs	https://doi.org/10.1145/3316781.3317853
Publication status	Published - 2019 Jun 2
Event	56th Annual Design Automation Conference, DAC 2019 - Las Vegas, United States Duration: 2019 Jun 2 → 2019 Jun 6

Publication series

Name	Proceedings - Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	56th Annual Design Automation Conference, DAC 2019
Country/Territory	United States
City	Las Vegas
Period	19/6/2 → 19/6/6

Bibliographical note

Funding Information:
This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317.

Funding Information:
This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317. This work was completed when Nam Sung Kim was at the University of Illinois, Urbana-Champaign.

Publisher Copyright:
© 2019 Association for Computing Machinery.

All Science Journal Classification (ASJC) codes

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modelling and Simulation

Access to Document

10.1145/3316781.3317853

Cite this

@inproceedings{a5c193e4ce194d509496728ebefed21b,

title = "LL-PCM: Low-latency phase change memory architecture",

abstract = "PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can significantly degrade system performance. In this paper, we analyze a PCM implementation in depth, and identify the primary cause of PCM's long latency, i.e., a long interconnect (high resistance/capacitance) path between a cell and a sense-amp/writedriver. This in turn requires (1) a very large charge pump consuming: ∼20% of PCM chip space, ∼50% of latency of write operations, and ∼2× more power than a write operation itself; and (2) a large current sense-amp with long time to pre-charge the interconnect path. Then, we propose Low-Latency PCM (LLPCM) architecture. Our analysis shows that LL-PCM can give 119% higher performance and consume 43% lower memory energy than PCM for memory-intensive applications. LL-PCM is only ∼1% larger than PCM, as the cost of reducing the resistance/capacitance of the interconnect path is negated by its 4.1× smaller charge pump.",

author = "Kim, {Nam Sung} and Choungki Song and Cho, {Woo Young} and Jian Huang and Myoungsoo Jung",

note = "Funding Information: This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317. Funding Information: This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317. This work was completed when Nam Sung Kim was at the University of Illinois, Urbana-Champaign. Publisher Copyright: {\textcopyright} 2019 Association for Computing Machinery.; 56th Annual Design Automation Conference, DAC 2019 ; Conference date: 02-06-2019 Through 06-06-2019",

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Kim, NS, Song, C, Cho, WY, Huang, J & Jung, M 2019, LL-PCM: Low-latency phase change memory architecture. in Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019., a14, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., 56th Annual Design Automation Conference, DAC 2019, Las Vegas, United States, 19/6/2. https://doi.org/10.1145/3316781.3317853

LL-PCM: Low-latency phase change memory architecture. / Kim, Nam Sung; Song, Choungki; Cho, Woo Young et al.
Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. a14 (Proceedings - Design Automation Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317. Funding Information: This work was supported in part by NRF 2016R1C1B2015312, DOE DEAC02-05CH11231, NRF 2015M3C4A7065645, MemRay grant, and NSF CNS-1850317. This work was completed when Nam Sung Kim was at the University of Illinois, Urbana-Champaign. Publisher Copyright: © 2019 Association for Computing Machinery.

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N2 - PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can significantly degrade system performance. In this paper, we analyze a PCM implementation in depth, and identify the primary cause of PCM's long latency, i.e., a long interconnect (high resistance/capacitance) path between a cell and a sense-amp/writedriver. This in turn requires (1) a very large charge pump consuming: ∼20% of PCM chip space, ∼50% of latency of write operations, and ∼2× more power than a write operation itself; and (2) a large current sense-amp with long time to pre-charge the interconnect path. Then, we propose Low-Latency PCM (LLPCM) architecture. Our analysis shows that LL-PCM can give 119% higher performance and consume 43% lower memory energy than PCM for memory-intensive applications. LL-PCM is only ∼1% larger than PCM, as the cost of reducing the resistance/capacitance of the interconnect path is negated by its 4.1× smaller charge pump.

AB - PCM is a promising non-volatile memory technology, as it can offer a unique trade-off between density and latency compared with DRAM and flash memory. Albeit PCM is much faster than flash memory, it is still notably slower than DRAM, which can significantly degrade system performance. In this paper, we analyze a PCM implementation in depth, and identify the primary cause of PCM's long latency, i.e., a long interconnect (high resistance/capacitance) path between a cell and a sense-amp/writedriver. This in turn requires (1) a very large charge pump consuming: ∼20% of PCM chip space, ∼50% of latency of write operations, and ∼2× more power than a write operation itself; and (2) a large current sense-amp with long time to pre-charge the interconnect path. Then, we propose Low-Latency PCM (LLPCM) architecture. Our analysis shows that LL-PCM can give 119% higher performance and consume 43% lower memory energy than PCM for memory-intensive applications. LL-PCM is only ∼1% larger than PCM, as the cost of reducing the resistance/capacitance of the interconnect path is negated by its 4.1× smaller charge pump.

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M3 - Conference contribution

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LL-PCM: Low-latency phase change memory architecture

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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