LARECD: Low area overhead and reliable error correction DMR architecture

Hyunyul Lim; Taehyun Kim; Dongsu Lee; Sungho Kang

doi:10.1109/ISOCC.2017.8368812

LARECD: Low area overhead and reliable error correction DMR architecture

Hyunyul Lim, Taehyun Kim, Dongsu Lee, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Recent HPC system generally is composed of enormous amounts of GPUs. GPU-based HPC system makes a reliability problem from the absence of error detection unit in GPUs. For improving the reliability of GPU, dual modular redundancy(DMR) architecture is presented. However, current DMR architectures do not care much to the correction sequence. Therefore, the data hazard can occur during the recovery sequence. We present LARECD (Low Area overhead and Reliable Error Correction DMR) architecture. This architecture can secure the error correction sequence from the data hazard. Experimental result demonstrates the efficiency of LARECD architecture.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	27-28
Number of pages	2
ISBN (Electronic)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368812
Publication status	Published - 2018 May 29
Event	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of Duration: 2017 Nov 5 → 2017 Nov 8

Publication series

Name	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
Country/Territory	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

Bibliographical note

Publisher Copyright:
© 2017 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/ISOCC.2017.8368812

Cite this

Lim, H., Kim, T., Lee, D., & Kang, S. (2018). LARECD: Low area overhead and reliable error correction DMR architecture. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 27-28). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368812

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title = "LARECD: Low area overhead and reliable error correction DMR architecture",

abstract = "Recent HPC system generally is composed of enormous amounts of GPUs. GPU-based HPC system makes a reliability problem from the absence of error detection unit in GPUs. For improving the reliability of GPU, dual modular redundancy(DMR) architecture is presented. However, current DMR architectures do not care much to the correction sequence. Therefore, the data hazard can occur during the recovery sequence. We present LARECD (Low Area overhead and Reliable Error Correction DMR) architecture. This architecture can secure the error correction sequence from the data hazard. Experimental result demonstrates the efficiency of LARECD architecture.",

author = "Hyunyul Lim and Taehyun Kim and Dongsu Lee and Sungho Kang",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",

year = "2018",

month = may,

day = "29",

doi = "10.1109/ISOCC.2017.8368812",

language = "English",

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Lim, H, Kim, T, Lee, D & Kang, S 2018, LARECD: Low area overhead and reliable error correction DMR architecture. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 27-28, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368812

LARECD: Low area overhead and reliable error correction DMR architecture. / Lim, Hyunyul; Kim, Taehyun; Lee, Dongsu et al.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 27-28 (Proceedings - International SoC Design Conference 2017, ISOCC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - LARECD

T2 - 14th International SoC Design Conference, ISOCC 2017

AU - Lim, Hyunyul

AU - Kim, Taehyun

AU - Lee, Dongsu

AU - Kang, Sungho

PY - 2018/5/29

Y1 - 2018/5/29

N2 - Recent HPC system generally is composed of enormous amounts of GPUs. GPU-based HPC system makes a reliability problem from the absence of error detection unit in GPUs. For improving the reliability of GPU, dual modular redundancy(DMR) architecture is presented. However, current DMR architectures do not care much to the correction sequence. Therefore, the data hazard can occur during the recovery sequence. We present LARECD (Low Area overhead and Reliable Error Correction DMR) architecture. This architecture can secure the error correction sequence from the data hazard. Experimental result demonstrates the efficiency of LARECD architecture.

AB - Recent HPC system generally is composed of enormous amounts of GPUs. GPU-based HPC system makes a reliability problem from the absence of error detection unit in GPUs. For improving the reliability of GPU, dual modular redundancy(DMR) architecture is presented. However, current DMR architectures do not care much to the correction sequence. Therefore, the data hazard can occur during the recovery sequence. We present LARECD (Low Area overhead and Reliable Error Correction DMR) architecture. This architecture can secure the error correction sequence from the data hazard. Experimental result demonstrates the efficiency of LARECD architecture.

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M3 - Conference contribution

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T3 - Proceedings - International SoC Design Conference 2017, ISOCC 2017

SP - 27

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BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 5 November 2017 through 8 November 2017

ER -

LARECD: Low area overhead and reliable error correction DMR architecture

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