Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance

Byung Wook Min; Gabriel M. Rebeiz

doi:10.1109/RFIC.2007.380948

Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance

Byung Wook Min, Gabriel M. Rebeiz

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

22 Citations (Scopus)

Abstract

This paper presents 35 GHz single-pole-singlethrow (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 μm BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.

Original language	English
Title of host publication	Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
Pages	569-572
Number of pages	4
DOIs	https://doi.org/10.1109/RFIC.2007.380948
Publication status	Published - 2007
Event	2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 - Honolulu, HI, United States Duration: 2007 Jun 3 → 2007 Jun 5

Publication series

Name	Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)	1529-2517

Other

Other	2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007
Country/Territory	United States
City	Honolulu, HI
Period	07/6/3 → 07/6/5

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1109/RFIC.2007.380948

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Min, B. W., & Rebeiz, G. M. (2007). Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. In Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 (pp. 569-572). Article 4266496 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium). https://doi.org/10.1109/RFIC.2007.380948

@inproceedings{dd15bcb0537e4eb39afbd70c240943c1,

title = "Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance",

abstract = "This paper presents 35 GHz single-pole-singlethrow (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 μm BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.",

author = "Min, {Byung Wook} and Rebeiz, {Gabriel M.}",

year = "2007",

doi = "10.1109/RFIC.2007.380948",

language = "English",

isbn = "1424405319",

series = "Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium",

pages = "569--572",

booktitle = "Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007",

note = "2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007 ; Conference date: 03-06-2007 Through 05-06-2007",

}

Min, BW & Rebeiz, GM 2007, Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. in Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007., 4266496, Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, pp. 569-572, 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007, Honolulu, HI, United States, 07/6/3. https://doi.org/10.1109/RFIC.2007.380948

Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance. / Min, Byung Wook; Rebeiz, Gabriel M.
Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. 2007. p. 569-572 4266496 (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - This paper presents 35 GHz single-pole-singlethrow (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 μm BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.

AB - This paper presents 35 GHz single-pole-singlethrow (SPST) and single-pole-double-throw (SPDT) CMOS switches using a 0.13 μm BiCMOS process (IBM 8HP). The CMOS transistors are designed to have a high substrate resistance to minimize the insertion loss and improve power handling capability. The SPST/SPDT switches have a insertion loss of 1.8 dB/2.2 dB, respectively, and an input 1-dB compression point (P1dB) greater than 22 dBm. The isolation is greater than 30 dB at 35-40 GHz and is achieved using two parallel resonant networks. To our knowledge, this is the first demonstration of low-loss, high-isolation CMOS switches at Ka-band frequencies.

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Ka-band low-loss and high-isolation 0.13 μm CMOS SPST/SPDT switches using high substrate resistance

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