Abstract
A silicon single-photon avalanche diode (Si-SPAD) with a deep multiplication zone was fabricated using 0.11-<inline-formula> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula>m-CMOS technology. Deep n-well (DNW) implantation with three energy levels was performed to prepare a deep junction, and the highest breakdown voltage (<inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{BR}}$</tex-math> </inline-formula>) and lowest dark count rate (DCR) were obtained at the highest DNW implantation energy. In addition, devices with different structures were manufactured: a shallow junction, deep junction with mask DNW, deep junction with mask DNW without shallow trench isolation (STI), and deep junction with blank DNW. The blank DNW structure exhibited a lower edge breakdown risk and less deviation between samples compared to those of mask DNW structure in terms of the <inline-formula> <tex-math notation="LaTeX">$\textit{V}_{\text{BR}}$</tex-math> </inline-formula> and DCR. Moreover, a new edge breakdown risk was observed between DNW and p-well (PW) in the DNW blank structure, which could be alleviated by adjusting the PW sizes. According to the measurement results, the STI structure was preferable in terms of fill factor. Measurements were obtained from real fabricated test device structures, and technology computer-aided design (TCAD) for various factors associated with Si-SPADs with deep multiplication structures was performed.
| Original language | English |
|---|---|
| Pages (from-to) | 1-6 |
| Number of pages | 6 |
| Journal | IEEE Transactions on Electron Devices |
| DOIs | |
| Publication status | Published - 2022 Sept 1 |
Bibliographical note
Publisher Copyright:IEEE
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering