Intrinsic Capacitance based Multi bit Computing in Memory

Young Kyu Lee; Minjune Yeo; Seokhee Cho; Seong Ook Jung

doi:10.1109/ISOCC53507.2021.9613882

Intrinsic Capacitance based Multi bit Computing in Memory

Young Kyu Lee, Minjune Yeo, Seokhee Cho, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Computing in memory (CIM) technique is being researched for process multiply-And-Accumulate operation which is used in deep neural networks efficiently. Conventional CIM architecture only supports binary neural network which has lower accuracy. Some approaches use capacitor for multi bit operation. However, because capacitor has large size, the area efficiency of CIM macro is degraded. This paper proposes CIM macro structure that supports multi bit operation using parasitic capacitance of transistor. The proposed structure does not need additional capacitor and thus, it can achieve area efficient multi bit operation.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	361-362
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613882
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613882

Cite this

@inproceedings{939b675d91744d71b543e9db70f1cca2,

title = "Intrinsic Capacitance based Multi bit Computing in Memory",

abstract = "Computing in memory (CIM) technique is being researched for process multiply-And-Accumulate operation which is used in deep neural networks efficiently. Conventional CIM architecture only supports binary neural network which has lower accuracy. Some approaches use capacitor for multi bit operation. However, because capacitor has large size, the area efficiency of CIM macro is degraded. This paper proposes CIM macro structure that supports multi bit operation using parasitic capacitance of transistor. The proposed structure does not need additional capacitor and thus, it can achieve area efficient multi bit operation.",

keywords = "Computing in Memory, Deep Neural Networks, Multi bit Computing, SRAM",

author = "Lee, {Young Kyu} and Minjune Yeo and Seokhee Cho and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613882",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "361--362",

booktitle = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

address = "United States",

}

Lee, YK, Yeo, M, Cho, S & Jung, SO 2021, Intrinsic Capacitance based Multi bit Computing in Memory. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 361-362, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613882

Intrinsic Capacitance based Multi bit Computing in Memory. / Lee, Young Kyu; Yeo, Minjune; Cho, Seokhee et al.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 361-362 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Intrinsic Capacitance based Multi bit Computing in Memory

AU - Lee, Young Kyu

AU - Yeo, Minjune

AU - Cho, Seokhee

AU - Jung, Seong Ook

PY - 2021

Y1 - 2021

N2 - Computing in memory (CIM) technique is being researched for process multiply-And-Accumulate operation which is used in deep neural networks efficiently. Conventional CIM architecture only supports binary neural network which has lower accuracy. Some approaches use capacitor for multi bit operation. However, because capacitor has large size, the area efficiency of CIM macro is degraded. This paper proposes CIM macro structure that supports multi bit operation using parasitic capacitance of transistor. The proposed structure does not need additional capacitor and thus, it can achieve area efficient multi bit operation.

AB - Computing in memory (CIM) technique is being researched for process multiply-And-Accumulate operation which is used in deep neural networks efficiently. Conventional CIM architecture only supports binary neural network which has lower accuracy. Some approaches use capacitor for multi bit operation. However, because capacitor has large size, the area efficiency of CIM macro is degraded. This paper proposes CIM macro structure that supports multi bit operation using parasitic capacitance of transistor. The proposed structure does not need additional capacitor and thus, it can achieve area efficient multi bit operation.

KW - Computing in Memory

KW - Deep Neural Networks

KW - Multi bit Computing

KW - SRAM

UR - http://www.scopus.com/inward/record.url?scp=85123356184&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85123356184&partnerID=8YFLogxK

U2 - 10.1109/ISOCC53507.2021.9613882

DO - 10.1109/ISOCC53507.2021.9613882

M3 - Conference contribution

AN - SCOPUS:85123356184

T3 - Proceedings - International SoC Design Conference 2021, ISOCC 2021

SP - 361

EP - 362

BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 18th International System-on-Chip Design Conference, ISOCC 2021

Y2 - 6 October 2021 through 9 October 2021

ER -

Intrinsic Capacitance based Multi bit Computing in Memory

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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