Input polling arbitration mechanism for a gigabit packet switch

J. W. Son; Y. Y. Oh; H. T. Lee; J. Y. Lee; S. B. Lee

doi:10.1049/el:19961368

Input polling arbitration mechanism for a gigabit packet switch

J. W. Son, Y. Y. Oh, H. T. Lee, J. Y. Lee, S. B. Lee

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.

Original language	English
Pages (from-to)	2050-2051
Number of pages	2
Journal	Electronics Letters
Volume	32
Issue number	22
DOIs	https://doi.org/10.1049/el:19961368
Publication status	Published - 1996 Oct 24

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:19961368

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title = "Input polling arbitration mechanism for a gigabit packet switch",

abstract = "Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.",

author = "Son, {J. W.} and Oh, {Y. Y.} and Lee, {H. T.} and Lee, {J. Y.} and Lee, {S. B.}",

year = "1996",

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doi = "10.1049/el:19961368",

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AU - Lee, S. B.

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Y1 - 1996/10/24

N2 - Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.

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Input polling arbitration mechanism for a gigabit packet switch

Abstract

All Science Journal Classification (ASJC) codes

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