Input polling arbitration mechanism for a gigabit packet switch

J. W. Son, Y. Y. Oh, H. T. Lee, J. Y. Lee, S. B. Lee

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)


Two head of line (HOL) packet arbitration mechanisms in an input buffered gigabit packet switch are proposed. These mechanisms have significant advantages in simple implementation while their performances still remain at acceptable levels.

Original languageEnglish
Pages (from-to)2050-2051
Number of pages2
JournalElectronics Letters
Issue number22
Publication statusPublished - 1996 Oct 24

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


Dive into the research topics of 'Input polling arbitration mechanism for a gigabit packet switch'. Together they form a unique fingerprint.

Cite this