To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOx passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332cm2 · V-1 · s-1 at 0.05 MV/cm - a 2× enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3 × 103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface.
Bibliographical noteFunding Information:
Manuscript received October 10, 2006; revised February 5, 2007. This work was supported in part by Semiconductor Research Corporation (SRC), Defense Advanced Research Projects Agency (DARPA), Advanced Processing and Prototyping Center (AP2C), and Texas Advanced Technology Program (TATP). The review of this letter was arranged by Editor B. Yu. S. Joshi, J. C. Lee, and S. K. Banerjee are with Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA (e-mail: email@example.com). C. Krug, D. Heh, and J. W. Oh are with SEMATECH, Inc., Austin, TX 78741 USA. H. J. Na is with the Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA, and also with SEMATECH, Inc., Austin, TX 78741 USA. H. R. Harris is AMD assignee at SEMATECH, Inc., Austin, TX 78741 USA. P. D. Kirsch, B. H. Lee, and R. Jammy are IBM assignees at SEMATECH, Inc., Austin, TX 78741 USA. P. Majhi is Intel assignee at SEMATECH, Inc., Austin, TX 78741 USA. H.-H. Tseng is Freescale assignee at SEMATECH, Inc., Austin, TX 78741 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2007.893274 Fig. 1. EELS and EDXS elemental profiles across the Ge/SiOX/HfSiO/WN gate stack. Inset: Corresponding HRXTEM image. The SiOX and HfSiO thicknesses are 1.6 and 2.7 nm, respectively.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering