Improved Ge surface passivation with ultrathin SiOX enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack

Sachin Joshi; Cristiano Krug; Dawei Heh; Hoon Joo Na; Harlan R. Harris; Jung Woo Oh; Paul D. Kirsch; Prashant Majhi; Byoung Hun Lee; Hsing Huang Tseng; Raj Jammy; Jack C. Lee; Sanjay K. Banerjee

doi:10.1109/LED.2007.893274

Improved Ge surface passivation with ultrathin SiO_X enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack

Sachin Joshi, Cristiano Krug, Dawei Heh, Hoon Joo Na, Harlan R. Harris, Jung Woo Oh, Paul D. Kirsch, Prashant Majhi, Byoung Hun Lee, Hsing Huang Tseng, Raj Jammy, Jack C. Lee, Sanjay K. Banerjee

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

35 Citations (Scopus)

Abstract

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_x passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332cm² · V^-1 · s^-1 at 0.05 MV/cm - a 2× enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3 × 10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface.

Original language	English
Pages (from-to)	308-311
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	28
Issue number	4
DOIs	https://doi.org/10.1109/LED.2007.893274
Publication status	Published - 2007 Apr

Bibliographical note

Funding Information:
Manuscript received October 10, 2006; revised February 5, 2007. This work was supported in part by Semiconductor Research Corporation (SRC), Defense Advanced Research Projects Agency (DARPA), Advanced Processing and Prototyping Center (AP2C), and Texas Advanced Technology Program (TATP). The review of this letter was arranged by Editor B. Yu. S. Joshi, J. C. Lee, and S. K. Banerjee are with Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA (e-mail: joshi@ece.utexas.edu). C. Krug, D. Heh, and J. W. Oh are with SEMATECH, Inc., Austin, TX 78741 USA. H. J. Na is with the Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA, and also with SEMATECH, Inc., Austin, TX 78741 USA. H. R. Harris is AMD assignee at SEMATECH, Inc., Austin, TX 78741 USA. P. D. Kirsch, B. H. Lee, and R. Jammy are IBM assignees at SEMATECH, Inc., Austin, TX 78741 USA. P. Majhi is Intel assignee at SEMATECH, Inc., Austin, TX 78741 USA. H.-H. Tseng is Freescale assignee at SEMATECH, Inc., Austin, TX 78741 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2007.893274 Fig. 1. EELS and EDXS elemental profiles across the Ge/SiOX/HfSiO/WN gate stack. Inset: Corresponding HRXTEM image. The SiOX and HfSiO thicknesses are 1.6 and 2.7 nm, respectively.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/LED.2007.893274

Cite this

Joshi, S., Krug, C., Heh, D., Na, H. J., Harris, H. R., Oh, J. W., Kirsch, P. D., Majhi, P., Lee, B. H., Tseng, H. H., Jammy, R., Lee, J. C., & Banerjee, S. K. (2007). Improved Ge surface passivation with ultrathin SiO_X enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack. IEEE Electron Device Letters, 28(4), 308-311. https://doi.org/10.1109/LED.2007.893274

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title = "Improved Ge surface passivation with ultrathin SiOX enabling high-mobility surface channel pMOSFETs featuring a HfSiO/WN gate stack",

abstract = "To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiOx passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332cm2 · V-1 · s-1 at 0.05 MV/cm - a 2× enhancement over the universal Si/SiO2 mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an ION/IOFF ratio of 3 × 103 without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface.",

author = "Sachin Joshi and Cristiano Krug and Dawei Heh and Na, {Hoon Joo} and Harris, {Harlan R.} and Oh, {Jung Woo} and Kirsch, {Paul D.} and Prashant Majhi and Lee, {Byoung Hun} and Tseng, {Hsing Huang} and Raj Jammy and Lee, {Jack C.} and Banerjee, {Sanjay K.}",

note = "Funding Information: Manuscript received October 10, 2006; revised February 5, 2007. This work was supported in part by Semiconductor Research Corporation (SRC), Defense Advanced Research Projects Agency (DARPA), Advanced Processing and Prototyping Center (AP2C), and Texas Advanced Technology Program (TATP). The review of this letter was arranged by Editor B. Yu. S. Joshi, J. C. Lee, and S. K. Banerjee are with Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA (e-mail: joshi@ece.utexas.edu). C. Krug, D. Heh, and J. W. Oh are with SEMATECH, Inc., Austin, TX 78741 USA. H. J. Na is with the Microelectronics Research Center, University of Texas at Austin, Austin, TX 78758 USA, and also with SEMATECH, Inc., Austin, TX 78741 USA. H. R. Harris is AMD assignee at SEMATECH, Inc., Austin, TX 78741 USA. P. D. Kirsch, B. H. Lee, and R. Jammy are IBM assignees at SEMATECH, Inc., Austin, TX 78741 USA. P. Majhi is Intel assignee at SEMATECH, Inc., Austin, TX 78741 USA. H.-H. Tseng is Freescale assignee at SEMATECH, Inc., Austin, TX 78741 USA. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2007.893274 Fig. 1. EELS and EDXS elemental profiles across the Ge/SiOX/HfSiO/WN gate stack. Inset: Corresponding HRXTEM image. The SiOX and HfSiO thicknesses are 1.6 and 2.7 nm, respectively.",

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AU - Heh, Dawei

AU - Na, Hoon Joo

AU - Harris, Harlan R.

AU - Oh, Jung Woo

AU - Kirsch, Paul D.

AU - Majhi, Prashant

AU - Lee, Byoung Hun

AU - Tseng, Hsing Huang

AU - Jammy, Raj

AU - Lee, Jack C.

AU - Banerjee, Sanjay K.

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