Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions

Kwan Yong Lim, Se Aug Jang, Yong Soo Kim, Heung Jae Cho, Jae Geun Oh, Su Ock Chung, Sung Joon Lee, Woo Kyung Sun, Jai Bum Suh, Hong Seon Yang, Hyun Chul Sohn

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)


We studied the reliability characteristics of cell transistors with two-different type gate sidewall spacer structures (O/N vs. N/O/N) in terms of Fowler-Nordheim (F-N) or gate-induced drain leakage (GIDL) stress-immunity. Through gate oxide stress-induced leakage current (SILC), junction leakage, GIDL, and drain current-gate voltage (Id-Vg) measurements, it was observed that the GIDL stress condition had much more critical effects on the reliability of cell array transistors than the F-N stress. Particularly, it was also found that the GIDL stress-induced device degradation was severer in case of the N/O/N gate sidewall spacer than the O/N spacer. It is thought that the relatively poor reliability of the N/O/N is closely related to the trap generation near the interface of the re-oxidized SiO2/nitride at the gate bottom edge as well as the defect generation due to the sidewall nitride film stress.

Original languageEnglish
Pages (from-to)485-488
Number of pages4
JournalAnnual Proceedings - Reliability Physics (Symposium)
Publication statusPublished - 2004
Event2004 IEEE International Reliability Physics Symposium Proceedings, 42nd Annual - Phoenix, AZ., United States
Duration: 2004 Apr 252004 Apr 29

Bibliographical note

Funding Information:
The work in the laboratory of J.G. is supported by the SYNAPSIS Foundation, the Béatrice Ederer-Weber Stiftung, the Floshield Foundation and the Alzheimer’s Association (grant no. NIRG-15-363964). The laboratory of D.M. is supported by the Foundation Jérôme Lejeune, Spanish Ministerio de Educación y Competitividad (grant no. BFU2014-53093). The laboratory of J.P.-T. is supported by the Spanish Ministerio de Economía, Industria y Competitividad and the FEDER programme from the EU (grant no. SAF2014-59469-R) and the CIBERNED. J.V.S.-M. is supported by a SYNAPSIS Foundation Fellowship for Advanced PostDocs and the Heidi Seiler-Stiftung foundation. H.H. is a Miguel Servet (CP14/00229) researcher funded by the Spanish Institute of Health Carlos III (ISCIII). B.A.S. is an EMBO long-term fellow (ALTF 1605-2014, Marie Curie Actions, LTFCOFUND2013, GA-2013-609409). A.M.-S. is a recipient of a FPI PhD studentship from MINECO. M.E. is an ICREA Research Professor. J.G. is an MQ fellow and a NARSAD Independent Investigator.

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality


Dive into the research topics of 'Impact of gate sidewall spacer structures on DRAM cell transistors under Fowler-Nordheim and gate-induced drain leakage stress conditions'. Together they form a unique fingerprint.

Cite this