TY - GEN
T1 - Highly optimized intra prediction architecture for high resolution application
AU - Choi, Jinha
AU - Yu, Jeyun
AU - Kim, Jaeseok
PY - 2010
Y1 - 2010
N2 - This paper proposes a new intra prediction architecture for high resolution applications. The standard intra prediction has a data dependency for the pipelined processing. To enable the pipelined intra prediction architecture, processing order changing methods and additional processing schedulers are proposed. However, previous methods are not considered for the parallel processing which is a key issue of high resolution applications, such as High Definition videos or Ultra High Definition videos. The proposed intra prediction architecture has a new scheduler and two difference calculation processing units for the high performance parallel processing in intra 44 luminance prediction and intra 8x8 luminance prediction. The proposed architecture reduces processing time by about 43.40% compared with the standard and by about 20.10% compared with previous architecture.
AB - This paper proposes a new intra prediction architecture for high resolution applications. The standard intra prediction has a data dependency for the pipelined processing. To enable the pipelined intra prediction architecture, processing order changing methods and additional processing schedulers are proposed. However, previous methods are not considered for the parallel processing which is a key issue of high resolution applications, such as High Definition videos or Ultra High Definition videos. The proposed intra prediction architecture has a new scheduler and two difference calculation processing units for the high performance parallel processing in intra 44 luminance prediction and intra 8x8 luminance prediction. The proposed architecture reduces processing time by about 43.40% compared with the standard and by about 20.10% compared with previous architecture.
UR - http://www.scopus.com/inward/record.url?scp=79959253763&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79959253763&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2010.5775074
DO - 10.1109/APCCAS.2010.5775074
M3 - Conference contribution
AN - SCOPUS:79959253763
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 390
EP - 393
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -