Highly manufacturable and high performance SDR/DDR 4Gb DRAM

K. N. Kim; H. S. Jeong; W. S. Yang; Y. S. Hwang; C. H. Cho; M. M. Jeong; S. Park; S. J. Ahn; Y. S. Chun; S. H. Shin; J. S. Park; S. H. Song; J. Y. Lee; S. M. Jang; C. H. Lee; J. H. Jeong; M. H. Cho; H. I. Yoon; J. S. Jeon

Highly manufacturable and high performance SDR/DDR 4Gb DRAM

K. N. Kim, H. S. Jeong, W. S. Yang, Y. S. Hwang, C. H. Cho, M. M. Jeong, S. Park, S. J. Ahn, Y. S. Chun, S. H. Shin, J. S. Park, S. H. Song, J. Y. Lee, S. M. Jang, C. H. Lee, J. H. Jeong, M. H. Cho, H. I. Yoon, J. S. Jeon

Research output: Contribution to conference › Paper › peer-review

7 Citations (Scopus)

Abstract

A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL₂O₃ MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

Original language	English
Pages	7-8
Number of pages	2
Publication status	Published - 2001
Event	2001 VLSI Technology Symposium - Kyoto, Japan Duration: 2001 Jun 12 → 2001 Jun 14

Other

Other	2001 VLSI Technology Symposium
Country/Territory	Japan
City	Kyoto
Period	01/6/12 → 01/6/14

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

Kim, K. N., Jeong, H. S., Yang, W. S., Hwang, Y. S., Cho, C. H., Jeong, M. M., Park, S., Ahn, S. J., Chun, Y. S., Shin, S. H., Park, J. S., Song, S. H., Lee, J. Y., Jang, S. M., Lee, C. H., Jeong, J. H., Cho, M. H., Yoon, H. I., & Jeon, J. S. (2001). Highly manufacturable and high performance SDR/DDR 4Gb DRAM. 7-8. Paper presented at 2001 VLSI Technology Symposium, Kyoto, Japan.

@conference{59ee61ece78d4e43a04ef9f98a5ba92a,

title = "Highly manufacturable and high performance SDR/DDR 4Gb DRAM",

abstract = "A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.",

author = "Kim, {K. N.} and Jeong, {H. S.} and Yang, {W. S.} and Hwang, {Y. S.} and Cho, {C. H.} and Jeong, {M. M.} and S. Park and Ahn, {S. J.} and Chun, {Y. S.} and Shin, {S. H.} and Park, {J. S.} and Song, {S. H.} and Lee, {J. Y.} and Jang, {S. M.} and Lee, {C. H.} and Jeong, {J. H.} and Cho, {M. H.} and Yoon, {H. I.} and Jeon, {J. S.}",

year = "2001",

language = "English",

pages = "7--8",

note = "2001 VLSI Technology Symposium ; Conference date: 12-06-2001 Through 14-06-2001",

}

TY - CONF

T1 - Highly manufacturable and high performance SDR/DDR 4Gb DRAM

AU - Kim, K. N.

AU - Jeong, H. S.

AU - Yang, W. S.

AU - Hwang, Y. S.

AU - Cho, C. H.

AU - Jeong, M. M.

AU - Park, S.

AU - Ahn, S. J.

AU - Chun, Y. S.

AU - Shin, S. H.

AU - Park, J. S.

AU - Song, S. H.

AU - Lee, J. Y.

AU - Jang, S. M.

AU - Lee, C. H.

AU - Jeong, J. H.

AU - Cho, M. H.

AU - Yoon, H. I.

AU - Jeon, J. S.

PY - 2001

Y1 - 2001

N2 - A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

AB - A HGB SDR/DDR high density dynamic random access storage (DRAM) was fabricated using with CMOS technology. The key technologies developed for this DRAM were KrF lithography with RET, novel ILD gap filling , full SAC with LSC, novel W-BL, low temperature AL2O3 MIS capacitor and triple CVD-AL interconnection technology. 80nm array transistor, sub-80nm memory cell contact and mechanically robust capacitor were developed to get rid of the single twin bit failures.

UR - http://www.scopus.com/inward/record.url?scp=0034793533&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034793533&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0034793533

SP - 7

EP - 8

T2 - 2001 VLSI Technology Symposium

Y2 - 12 June 2001 through 14 June 2001

ER -

Highly manufacturable and high performance SDR/DDR 4Gb DRAM

Abstract

Other

All Science Journal Classification (ASJC) codes

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