High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit

Dong Han Ko; Sehee Lim; Young Kyu Lee; Seong Ook Jung

doi:10.1109/ISOCC53507.2021.9613886

High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit

Dong Han Ko, Sehee Lim, Young Kyu Lee, Seong Ook Jung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The emerging nonvolatile memory (NVM)-based logic in-memory (LiM) structure can reduce power consumption caused by data transfer since it integrates memory and logic units very closely. The ferroelectric field-effect transistor (FeFET) is one of the promising candidates for NVM-based LiM structure owing to its unique characteristics: Three-Terminal structure and high ION/OFF ratio. In this paper, we propose the FeFET based reconfigurable logic circuit which can provide AND/OR/XOR logic value in a single circuit. Simulation results show that it can achieve a 67% lower transistor number, 17% faster delay, and 54% less energy than STT-MTJ based reconfigurable logic circuit.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2021, ISOCC 2021
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	321-322
Number of pages	2
ISBN (Electronic)	9781665401746
DOIs	https://doi.org/10.1109/ISOCC53507.2021.9613886
Publication status	Published - 2021
Event	18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of Duration: 2021 Oct 6 → 2021 Oct 9

Publication series

Name	Proceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference	18th International System-on-Chip Design Conference, ISOCC 2021
Country/Territory	Korea, Republic of
City	Jeju Island
Period	21/10/6 → 21/10/9

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Information Systems
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISOCC53507.2021.9613886

Cite this

Ko, D. H., Lim, S., Lee, Y. K., & Jung, S. O. (2021). High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. In Proceedings - International SoC Design Conference 2021, ISOCC 2021 (pp. 321-322). (Proceedings - International SoC Design Conference 2021, ISOCC 2021). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC53507.2021.9613886

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title = "High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit",

abstract = "The emerging nonvolatile memory (NVM)-based logic in-memory (LiM) structure can reduce power consumption caused by data transfer since it integrates memory and logic units very closely. The ferroelectric field-effect transistor (FeFET) is one of the promising candidates for NVM-based LiM structure owing to its unique characteristics: Three-Terminal structure and high ION/OFF ratio. In this paper, we propose the FeFET based reconfigurable logic circuit which can provide AND/OR/XOR logic value in a single circuit. Simulation results show that it can achieve a 67% lower transistor number, 17% faster delay, and 54% less energy than STT-MTJ based reconfigurable logic circuit.",

keywords = "ferroelectic field-effect transistor, logic-in memory, nonvolatile memory, reconfigurable logic",

author = "Ko, {Dong Han} and Sehee Lim and Lee, {Young Kyu} and Jung, {Seong Ook}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 18th International System-on-Chip Design Conference, ISOCC 2021 ; Conference date: 06-10-2021 Through 09-10-2021",

year = "2021",

doi = "10.1109/ISOCC53507.2021.9613886",

language = "English",

series = "Proceedings - International SoC Design Conference 2021, ISOCC 2021",

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Ko, DH, Lim, S, Lee, YK & Jung, SO 2021, High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. in Proceedings - International SoC Design Conference 2021, ISOCC 2021. Proceedings - International SoC Design Conference 2021, ISOCC 2021, Institute of Electrical and Electronics Engineers Inc., pp. 321-322, 18th International System-on-Chip Design Conference, ISOCC 2021, Jeju Island, Korea, Republic of, 21/10/6. https://doi.org/10.1109/ISOCC53507.2021.9613886

High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. / Ko, Dong Han; Lim, Sehee; Lee, Young Kyu et al.
Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc., 2021. p. 321-322 (Proceedings - International SoC Design Conference 2021, ISOCC 2021).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit

AU - Ko, Dong Han

AU - Lim, Sehee

AU - Lee, Young Kyu

AU - Jung, Seong Ook

PY - 2021

Y1 - 2021

N2 - The emerging nonvolatile memory (NVM)-based logic in-memory (LiM) structure can reduce power consumption caused by data transfer since it integrates memory and logic units very closely. The ferroelectric field-effect transistor (FeFET) is one of the promising candidates for NVM-based LiM structure owing to its unique characteristics: Three-Terminal structure and high ION/OFF ratio. In this paper, we propose the FeFET based reconfigurable logic circuit which can provide AND/OR/XOR logic value in a single circuit. Simulation results show that it can achieve a 67% lower transistor number, 17% faster delay, and 54% less energy than STT-MTJ based reconfigurable logic circuit.

AB - The emerging nonvolatile memory (NVM)-based logic in-memory (LiM) structure can reduce power consumption caused by data transfer since it integrates memory and logic units very closely. The ferroelectric field-effect transistor (FeFET) is one of the promising candidates for NVM-based LiM structure owing to its unique characteristics: Three-Terminal structure and high ION/OFF ratio. In this paper, we propose the FeFET based reconfigurable logic circuit which can provide AND/OR/XOR logic value in a single circuit. Simulation results show that it can achieve a 67% lower transistor number, 17% faster delay, and 54% less energy than STT-MTJ based reconfigurable logic circuit.

KW - ferroelectic field-effect transistor

KW - logic-in memory

KW - nonvolatile memory

KW - reconfigurable logic

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BT - Proceedings - International SoC Design Conference 2021, ISOCC 2021

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Ko DH, Lim S, Lee YK, Jung SO. High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. In Proceedings - International SoC Design Conference 2021, ISOCC 2021. Institute of Electrical and Electronics Engineers Inc. 2021. p. 321-322. (Proceedings - International SoC Design Conference 2021, ISOCC 2021). doi: 10.1109/ISOCC53507.2021.9613886

High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit

Abstract

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