High-efficiency memory BISR with two serial RA stages using spare memories

I. Kang; W. Jeong; S. Kang

doi:10.1049/el:20083611

High-efficiency memory BISR with two serial RA stages using spare memories

I. Kang, W. Jeong, S. Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

As technology has become more advanced, the density of memory has increased greatly. This development has led to need for a high-efficiency redundancy analysis (RA) algorithm to improve yield rate. Presented is a new methodology that can achieve high-efficiency repair against faults in memory. Experimental results show that the proposed built-in self-repair (BISR) method performs well.

Original language	English
Pages (from-to)	515-517
Number of pages	3
Journal	Electronics Letters
Volume	44
Issue number	8
DOIs	https://doi.org/10.1049/el:20083611
Publication status	Published - 2008

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1049/el:20083611

Cite this

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title = "High-efficiency memory BISR with two serial RA stages using spare memories",

abstract = "As technology has become more advanced, the density of memory has increased greatly. This development has led to need for a high-efficiency redundancy analysis (RA) algorithm to improve yield rate. Presented is a new methodology that can achieve high-efficiency repair against faults in memory. Experimental results show that the proposed built-in self-repair (BISR) method performs well.",

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journal = "Electronics Letters",

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AU - Kang, I.

AU - Jeong, W.

AU - Kang, S.

PY - 2008

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AB - As technology has become more advanced, the density of memory has increased greatly. This development has led to need for a high-efficiency redundancy analysis (RA) algorithm to improve yield rate. Presented is a new methodology that can achieve high-efficiency repair against faults in memory. Experimental results show that the proposed built-in self-repair (BISR) method performs well.

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DO - 10.1049/el:20083611

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SP - 515

EP - 517

JO - Electronics Letters

JF - Electronics Letters

IS - 8

ER -

High-efficiency memory BISR with two serial RA stages using spare memories

Abstract

All Science Journal Classification (ASJC) codes

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