High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond

H. J. Oh; J. Y. Kim; J. H. Kim; S. G. Park; D. H. Kim; S. E. Kim; D. S. Woo; Y. S. Lee; G. W. Ha; J. M. Park; N. J. Kang; H. J. Kim; Y. S. Hwang; B. Y. Kim; D. I. Kim; Y. S. Cho; J. K. Choi; B. H. Lee; S. B. Kim; M. H. Cho; Y. I. Kim; J. Choi; D. W. Shin; M. S. Shim; W. T. Choi; G. P. Lee; Y. J. Park; W. S. Lee; B. I. Ryu

doi:10.1109/ESSDER.2005.1546614

High-density low-power-operating DRAM device adopting 6F² cell scheme with novel S-RCAT structure on 80nm feature size and beyond

H. J. Oh, J. Y. Kim, J. H. Kim, S. G. Park, D. H. Kim, S. E. Kim, D. S. Woo, Y. S. Lee, G. W. Ha, J. M. Park, N. J. Kang, H. J. Kim, Y. S. Hwang, B. Y. Kim, D. I. Kim, Y. S. Cho, J. K. Choi, B. H. Lee, S. B. Kim, M. H. ChoY. I. Kim, J. Choi, D. W. Shin, M. S. Shim, W. T. Choi, G. P. Lee, Y. J. Park, W. S. Lee, B. I. Ryu

Department of Physics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Citations (Scopus)

Abstract

For the first time, the DRAM device composed of 6F² open-bit-line memory cell with 80nm feature size is developed. Adopting 6F ² scheme instead of customary 8F² scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F² accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F ², TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V_th so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) is introduced. It is the improved scheme of RCAT used in 8F² scheme. By adopting S-RCAT, V_th can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

Original language	English
Title of host publication	Proceedings of ESSDERC 2005
Subtitle of host publication	35th European Solid-State Device Research Conference
Pages	177-180
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDER.2005.1546614
Publication status	Published - 2005
Event	ESSDERC 2005: 35th European Solid-State Device Research Conference - Grenoble, France Duration: 2005 Sept 12 → 2005 Sept 16

Publication series

Name	Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference
Volume	2005

Other

Other	ESSDERC 2005: 35th European Solid-State Device Research Conference
Country/Territory	France
City	Grenoble
Period	05/9/12 → 05/9/16

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/ESSDER.2005.1546614

Cite this

Oh, H. J., Kim, J. Y., Kim, J. H., Park, S. G., Kim, D. H., Kim, S. E., Woo, D. S., Lee, Y. S., Ha, G. W., Park, J. M., Kang, N. J., Kim, H. J., Hwang, Y. S., Kim, B. Y., Kim, D. I., Cho, Y. S., Choi, J. K., Lee, B. H., Kim, S. B., ... Ryu, B. I. (2005). High-density low-power-operating DRAM device adopting 6F² cell scheme with novel S-RCAT structure on 80nm feature size and beyond. In Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference (pp. 177-180). [1546614] (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference; Vol. 2005). https://doi.org/10.1109/ESSDER.2005.1546614

@inproceedings{c0bfa1e664e6413ca72959a7cd1a3f79,

title = "High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond",

abstract = "For the first time, the DRAM device composed of 6F2 open-bit-line memory cell with 80nm feature size is developed. Adopting 6F 2 scheme instead of customary 8F2 scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F2 accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F 2, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell Vth so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) is introduced. It is the improved scheme of RCAT used in 8F2 scheme. By adopting S-RCAT, Vth can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.",

author = "Oh, {H. J.} and Kim, {J. Y.} and Kim, {J. H.} and Park, {S. G.} and Kim, {D. H.} and Kim, {S. E.} and Woo, {D. S.} and Lee, {Y. S.} and Ha, {G. W.} and Park, {J. M.} and Kang, {N. J.} and Kim, {H. J.} and Hwang, {Y. S.} and Kim, {B. Y.} and Kim, {D. I.} and Cho, {Y. S.} and Choi, {J. K.} and Lee, {B. H.} and Kim, {S. B.} and Cho, {M. H.} and Kim, {Y. I.} and J. Choi and Shin, {D. W.} and Shim, {M. S.} and Choi, {W. T.} and Lee, {G. P.} and Park, {Y. J.} and Lee, {W. S.} and Ryu, {B. I.}",

year = "2005",

doi = "10.1109/ESSDER.2005.1546614",

language = "English",

isbn = "0780392035",

series = "Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference",

pages = "177--180",

booktitle = "Proceedings of ESSDERC 2005",

note = "ESSDERC 2005: 35th European Solid-State Device Research Conference ; Conference date: 12-09-2005 Through 16-09-2005",

}

Oh, HJ, Kim, JY, Kim, JH, Park, SG, Kim, DH, Kim, SE, Woo, DS, Lee, YS, Ha, GW, Park, JM, Kang, NJ, Kim, HJ, Hwang, YS, Kim, BY, Kim, DI, Cho, YS, Choi, JK, Lee, BH, Kim, SB, Cho, MH, Kim, YI, Choi, J, Shin, DW, Shim, MS, Choi, WT, Lee, GP, Park, YJ, Lee, WS & Ryu, BI 2005, High-density low-power-operating DRAM device adopting 6F² cell scheme with novel S-RCAT structure on 80nm feature size and beyond. in Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference., 1546614, Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference, vol. 2005, pp. 177-180, ESSDERC 2005: 35th European Solid-State Device Research Conference, Grenoble, France, 05/9/12. https://doi.org/10.1109/ESSDER.2005.1546614

High-density low-power-operating DRAM device adopting 6F² cell scheme with novel S-RCAT structure on 80nm feature size and beyond. / Oh, H. J.; Kim, J. Y.; Kim, J. H. et al.
Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference. 2005. p. 177-180 1546614 (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference; Vol. 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - High-density low-power-operating DRAM device adopting 6F2 cell scheme with novel S-RCAT structure on 80nm feature size and beyond

AU - Oh, H. J.

AU - Kim, J. Y.

AU - Kim, J. H.

AU - Park, S. G.

AU - Kim, D. H.

AU - Kim, S. E.

AU - Woo, D. S.

AU - Lee, Y. S.

AU - Ha, G. W.

AU - Park, J. M.

AU - Kang, N. J.

AU - Kim, H. J.

AU - Hwang, Y. S.

AU - Kim, B. Y.

AU - Kim, D. I.

AU - Cho, Y. S.

AU - Choi, J. K.

AU - Lee, B. H.

AU - Kim, S. B.

AU - Cho, M. H.

AU - Kim, Y. I.

AU - Choi, J.

AU - Shin, D. W.

AU - Shim, M. S.

AU - Choi, W. T.

AU - Lee, G. P.

AU - Park, Y. J.

AU - Lee, W. S.

AU - Ryu, B. I.

PY - 2005

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N2 - For the first time, the DRAM device composed of 6F2 open-bit-line memory cell with 80nm feature size is developed. Adopting 6F 2 scheme instead of customary 8F2 scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F2 accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F 2, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell Vth so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) is introduced. It is the improved scheme of RCAT used in 8F2 scheme. By adopting S-RCAT, Vth can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

AB - For the first time, the DRAM device composed of 6F2 open-bit-line memory cell with 80nm feature size is developed. Adopting 6F 2 scheme instead of customary 8F2 scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F2 accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F 2, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell Vth so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) is introduced. It is the improved scheme of RCAT used in 8F2 scheme. By adopting S-RCAT, Vth can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

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Oh HJ, Kim JY, Kim JH, Park SG, Kim DH, Kim SE et al. High-density low-power-operating DRAM device adopting 6F² cell scheme with novel S-RCAT structure on 80nm feature size and beyond. In Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference. 2005. p. 177-180. 1546614. (Proceedings of ESSDERC 2005: 35th European Solid-State Device Research Conference). doi: 10.1109/ESSDER.2005.1546614