HiDISC: A decoupled architecture for data-intensive applications

Won W. Ro; Jean Luc Gaudiot; Stephen P. Crago; Alvin M. Despain

doi:10.1109/IPDPS.2003.1213076

HiDISC: A decoupled architecture for data-intensive applications

Won W. Ro, Jean Luc Gaudiot, Stephen P. Crago, Alvin M. Despain

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching techniques at both the hardware and the software levels. Three processors, one for each level of the memory hierarchy, act in concert to mask the memory latency. Our performance evaluation benchmarks include the Data-Intensive Systems Benchmark suite and the DIS Stressmark suite. Our simulation results point to a distinct advantage of the HiDISC system over current prevailing superscalar architectures for both sets of the benchmarks. On the average, a 12% improvement in performance is achieved while 17% of cache misses are eliminated.

Original language	English
Title of host publication	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	0769519261, 9780769519265
DOIs	https://doi.org/10.1109/IPDPS.2003.1213076
Publication status	Published - 2003
Event	International Parallel and Distributed Processing Symposium, IPDPS 2003 - Nice, France Duration: 2003 Apr 22 → 2003 Apr 26

Publication series

Name	Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Other

Other	International Parallel and Distributed Processing Symposium, IPDPS 2003
Country/Territory	France
City	Nice
Period	03/4/22 → 03/4/26

Bibliographical note

Publisher Copyright:
© 2003 IEEE.

All Science Journal Classification (ASJC) codes

Computational Theory and Mathematics
Theoretical Computer Science
Software

Access to Document

10.1109/IPDPS.2003.1213076

Cite this

Ro, W. W., Gaudiot, J. L., Crago, S. P., & Despain, A. M. (2003). HiDISC: A decoupled architecture for data-intensive applications. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003 Article 1213076 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPS.2003.1213076

@inproceedings{6717d3dd398740e0b9c351168448402b,

title = "HiDISC: A decoupled architecture for data-intensive applications",

abstract = "This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching techniques at both the hardware and the software levels. Three processors, one for each level of the memory hierarchy, act in concert to mask the memory latency. Our performance evaluation benchmarks include the Data-Intensive Systems Benchmark suite and the DIS Stressmark suite. Our simulation results point to a distinct advantage of the HiDISC system over current prevailing superscalar architectures for both sets of the benchmarks. On the average, a 12% improvement in performance is achieved while 17% of cache misses are eliminated.",

author = "Ro, {Won W.} and Gaudiot, {Jean Luc} and Crago, {Stephen P.} and Despain, {Alvin M.}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; International Parallel and Distributed Processing Symposium, IPDPS 2003 ; Conference date: 22-04-2003 Through 26-04-2003",

year = "2003",

doi = "10.1109/IPDPS.2003.1213076",

language = "English",

series = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003",

address = "United States",

}

Ro, WW, Gaudiot, JL, Crago, SP & Despain, AM 2003, HiDISC: A decoupled architecture for data-intensive applications. in Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003., 1213076, Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003, Institute of Electrical and Electronics Engineers Inc., International Parallel and Distributed Processing Symposium, IPDPS 2003, Nice, France, 03/4/22. https://doi.org/10.1109/IPDPS.2003.1213076

HiDISC: A decoupled architecture for data-intensive applications. / Ro, Won W.; Gaudiot, Jean Luc; Crago, Stephen P. et al.
Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc., 2003. 1213076 (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - HiDISC

T2 - International Parallel and Distributed Processing Symposium, IPDPS 2003

AU - Ro, Won W.

AU - Gaudiot, Jean Luc

AU - Crago, Stephen P.

AU - Despain, Alvin M.

PY - 2003

Y1 - 2003

N2 - This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching techniques at both the hardware and the software levels. Three processors, one for each level of the memory hierarchy, act in concert to mask the memory latency. Our performance evaluation benchmarks include the Data-Intensive Systems Benchmark suite and the DIS Stressmark suite. Our simulation results point to a distinct advantage of the HiDISC system over current prevailing superscalar architectures for both sets of the benchmarks. On the average, a 12% improvement in performance is achieved while 17% of cache misses are eliminated.

AB - This paper presents the design and performance evaluation of our high-performance decoupled architecture, the HiDISC (Hierarchical Decoupled Instruction Stream Computer). HiDISC provides low memory access latency by introducing enhanced data prefetching techniques at both the hardware and the software levels. Three processors, one for each level of the memory hierarchy, act in concert to mask the memory latency. Our performance evaluation benchmarks include the Data-Intensive Systems Benchmark suite and the DIS Stressmark suite. Our simulation results point to a distinct advantage of the HiDISC system over current prevailing superscalar architectures for both sets of the benchmarks. On the average, a 12% improvement in performance is achieved while 17% of cache misses are eliminated.

UR - http://www.scopus.com/inward/record.url?scp=33749498429&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33749498429&partnerID=8YFLogxK

U2 - 10.1109/IPDPS.2003.1213076

DO - 10.1109/IPDPS.2003.1213076

M3 - Conference contribution

AN - SCOPUS:33749498429

T3 - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

BT - Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 22 April 2003 through 26 April 2003

ER -

Ro WW, Gaudiot JL, Crago SP, Despain AM. HiDISC: A decoupled architecture for data-intensive applications. In Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003. Institute of Electrical and Electronics Engineers Inc. 2003. 1213076. (Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003). doi: 10.1109/IPDPS.2003.1213076

HiDISC: A decoupled architecture for data-intensive applications

Abstract

Publication series

Other

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this