Hardware implementation of a tessellation accelerator for the openVG standard

Seung Hun Kim, Yunho Oh, Karam Park, Won Woo Ro

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)


The OpenVG standard has been introduced as an efficient vector graphics API for embedded systems. There have been several OpenVG implementations that are based on the software rendering of image. However, the software rendering needs more execution time and power consumption than hardware accelerated rendering. For the efficient hardware implementation, we merge eight pipeline stages in the original specification to four pipeline stages. The first hardware acceleration stage is the tessellation part which is one of the pipeline stages that calculates the edge of vector graphics. In this paper, we provide an efficient hardware design for the tessellation stage and claim this would eventually reduce the execution time and hardware complexity.

Original languageEnglish
Pages (from-to)440-446
Number of pages7
Journalieice electronics express
Issue number6
Publication statusPublished - 2010 Mar 25

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering


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