Hardware Efficient Built-in Self-Test Architecture for Power and Ground TSVs in 3D IC

Donghyun Han, Youngkwang Lee, Sooryeong Lee, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

3D integrated circuits (3D ICs) based on through-silicon vias (TSVs) are widely used as a solution to solve the interconnect and power problems in IC design. However, as the structures of 3D ICs become more complex, testing has emerged as an important challenge. It is difficult to test power and ground TSVs because they are connected to a grid after stacking. In this paper, a built-in self-Test architecture for power and ground TSVs is proposed. This architecture tests for three types of TSV faults that are critical to the operation of TSVs. The proposed test architecture can improve the reliability of 3D stacked IC by providing a suitable test for power and ground TSVs with little hardware overhead.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2021, ISOCC 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages101-102
Number of pages2
ISBN (Electronic)9781665401746
DOIs
Publication statusPublished - 2021
Event18th International System-on-Chip Design Conference, ISOCC 2021 - Jeju Island, Korea, Republic of
Duration: 2021 Oct 62021 Oct 9

Publication series

NameProceedings - International SoC Design Conference 2021, ISOCC 2021

Conference

Conference18th International System-on-Chip Design Conference, ISOCC 2021
Country/TerritoryKorea, Republic of
CityJeju Island
Period21/10/621/10/9

Bibliographical note

Publisher Copyright:
© 2021 IEEE.

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Information Systems
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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