Hardware-Efficient Built-In Redundancy Analysis for Memory with Various Spares

Jooyoung Kim, Woosung Lee, Keewon Cho, Sungho Kang

Research output: Contribution to journalArticlepeer-review

18 Citations (Scopus)


Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy analysis (BIRA) is of utmost importance because the probability of fault occurrence increases with a larger memory capacity. A traditional spare structure that consists of simple rows and columns is somewhat inadequate for multiple memory blocks BIRA because the hardware overhead and spare allocation efficiency are degraded. The proposed BIRA uses various types of spares and can achieve a higher yield than a simple row and column spare structure. Herein, we propose a BIRA that can achieve an optimal repair rate using various spare types. The proposed analyzer can exhaustively search not only row and column spare types but also global and local spare types. In addition, this paper proposes a fault-storing content-addressable memory (CAM) structure. The proposed CAM is small and collects faults efficiently. The experimental results show a high repair rate with a small hardware overhead and a short analysis time.

Original languageEnglish
Article number7572978
Pages (from-to)844-856
Number of pages13
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number3
Publication statusPublished - 2017 Mar

Bibliographical note

Publisher Copyright:
© 2016 IEEE.

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering


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