Hardware design of motion data decoding process for H.264/AVC

Kiwon Yoo, Kwanghoon Sohn

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


In H.264/AVC, motion data can be basically derived by the following two schemes: one is a typical spatial prediction scheme based on the DPCM and the other is a sophisticated spatiotemporal prediction scheme for the skipped motion data, formally referred to as a direct mode. We verified through instruction level profiling that when these schemes are combined with various H.264/AVC coding techniques, the computational burden to derive the motion data could be considerably aggravated. Specifically, its computational complexity amounts to maximally 55% of that of the overall syntax parsing process. In this paper, we aim at an efficient hardware design of the motion data decoding process for H.264/AVC, for which all the key design considerations are addressed in detail and respective rational answers are presented. As comparing the resulting hardware design with the processor-based solution, its effectiveness was clearly demonstrated. The proposed design was implemented with 43.2 K logic gates and three on-chip memories of 3584 bits using Samsung Semiconductor's Standard Cell Library in 65 nm L6LP process technology (SS65LP), and was capable of operating the H.264/AVC high-profile video bitstream of 1080p@60fps at 100 MHz consuming 843 μW. Crown

Original languageEnglish
Pages (from-to)208-223
Number of pages16
JournalSignal Processing: Image Communication
Issue number3
Publication statusPublished - 2010 Mar

Bibliographical note

Funding Information:
This research was supported by the MKE, Korea, under the ITRC support program supervised by the IITA ( IITA-2009-(C1090-0902-0011) .

All Science Journal Classification (ASJC) codes

  • Software
  • Signal Processing
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering


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