Hardware Accelerators in Embedded Systems

Jinhyuk Kim, Shiho Kim

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)

Abstract

The empirical law for embedded system design is that adding hardware increases a power requirement. However, with hardware accelerators, the traditional empirical rule rarely changes. Adding hardware can affect performance. Analyzing algorithms of programmable logic and implementing appropriate accelerators allow designers to increase design performance while reducing power consumption in embedded computing systems. Neuromorphic chips and neural processing units, also known as the intelligent processing unit, are special network application package processors that use a data-driven parallel computing architecture to process extensive multimedia data, especially video and images. We will look at two trends: General Purpose Graphics Processing Units and Neural Processing Units with central and graphics processing units. We are also going to review three commercialized hardware accelerators in embedded systems.

Original languageEnglish
Title of host publicationArtificial Intelligence and Hardware Accelerators
PublisherSpringer International Publishing
Pages167-181
Number of pages15
ISBN (Electronic)9783031221705
ISBN (Print)9783031221699
DOIs
Publication statusPublished - 2023 Jan 1

Bibliographical note

Publisher Copyright:
© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

All Science Journal Classification (ASJC) codes

  • General Engineering
  • General Computer Science

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